i need a simple vhdl code for dividing 23 bit dy 23 bit with clock input,divisor input,dividend input ,quotient and remainder input.............pls help

 

When is your assignment due and why are you not asking your professor for help?

 

professor asked us to do it on our own ......

 

So on your own means ask others for the answer?

 

no i searched for answers i got some ...if u can help then i can complete it

 

Without knowing where you are stuck and what you have thus far, it will be pretty hard to help you...

 

i donno wat to do wit the clock.......my teacher said each division operation must be carried at either of the edges ......i donno how to program dat

 

Well, let's start with what you do know regarding the topic.

What method are you supposed to be using? Combinational? Algorithm?

 

i donno wat to do wit the clock.......my teacher said each division operation must be carried at either of the edges ......i donno how to program dat

Look up clock process block in VHDL. The basic structure is thus:

process (clk, reset)
begin
  if reset = '1' then
    --program default reset values here
  elsif clk'event and clk = '1' then
    --edge defined values are programed here
  end if;
end process

See other examples here

http://stackoverflow.com/questions/9989913/vhdl-how-to-use-clk-and-reset-in-process

 

So on your own means ask others for the answer?

+1

The dance begins anew.