Hello ,I have built a PMOS device with Vt=-0.39 shown in the link bellow
Vs=1.8 Vg=-1.5
Vgs=-1.5-1.8=-3.3V
|Vgs-Vt|=|Vgs-Vt|=|-3.3-(-0.39)|=2.91>|Vds|=1.8
I get a result where no matter what is my Source voltage it will alway be in linear state.
although as you can see in the plot bellow i get a good result.
Where did i go wrong in the biasing condition of PMOS?
Thanks.
https://sanjayvidhyadharan.in/Downloads/tsmc_180_nm/tsmc018.lib
Vs=1.8 Vg=-1.5
Vgs=-1.5-1.8=-3.3V
|Vgs-Vt|=|Vgs-Vt|=|-3.3-(-0.39)|=2.91>|Vds|=1.8
I get a result where no matter what is my Source voltage it will alway be in linear state.
although as you can see in the plot bellow i get a good result.
Where did i go wrong in the biasing condition of PMOS?
Thanks.
https://sanjayvidhyadharan.in/Downloads/tsmc_180_nm/tsmc018.lib
