Hi,

For some hobbyist projects I would like to use UVM methodology for verification of my growing RTL design (and future designs hopefully).

Since this is hobbyst purpose (so purchasing highly expensive licenses (as Synopsys etc.) is out of scope, as of course using licences from my company for my hobbyist projects.

In mainly always used iverilog for my purpose because of having all in Verilog/System Verilog (without C, C++ etc.[1]). But now is becoming very limited for minimal serious verification since it still doesn't support classes neither randomization (not using $urandom_range) and coverage.

[1] It is true that commercial tools use C/C++ behind the scenes. Compiling with VCS generates a lot of C objects in obj dirs but this is hidden to the designer.

Vivado simulator seems really slow so initially I would like to avoid it if possible.. Also, even if has improved in the last few years, it still has many bugs due to its SW architecture IMO.

Possible solutions I came up with:

1) Use UVM SystemC Accellera libs with iverilog-vpi (which should be possible).

2) Use Accellera SystemC with SCV (not UVM but similar) and iverilog-vpi (example: https://github.com/Kenji-Ishimaru/scv_iv_sample).

3) As far as I know I could implement UVM monitors/drivers/scoreboards using Verilator, but I don't know much about UVM support so I have to test it before being sure of this. I successfully compiled Verilator so I will test during these days with SV UVM.

What's your experience with verification on these 3 environments tools (or others)? I would really appreciate to read them.

Thanks,
s.

 

You can start by lletting us know what you are actually asking about: " UVM methodology for verification " tells me absolutely nothing!! I am aware of "RTL", but never used it.
The fact is that some good software is terribly expensive, and tightly licensed.

 

"UVM methodology for verification" tells me absolutely nothing!!

UVM (Universal Verification Methodology) is a standardized methodology for verifying IC designs.

It is very huge argument to explain well in a post, not my professional job neither (I am a design engineer not a verification engineer [*]), but you can read something more about Verification and UVM on the following links:

https://www.cadence.com/en_US/home/explore/soc-verification.html
https://www.design-reuse.com/article/61360-soc-verification-flow-and-methodologies/
https://theartofverification.com/soc-verification-flow/
https://www.chipverify.com/tutorials/uvm

BTW I am testing Verilator (which in contrast to iverilog supports classes) with UVM support.

[*] Also, in professional environment a design engineer should not do verification (and normally don't), since having the two roles separated decrease the probability of having a buggy design and Tape-outs are very expensive.

 

The less common abbreviations and acronyms don't mean much to those of us not familiar with the design of logic IC devices. Certainly that is a very specific field of expertise that mos of us are quite unfamiliar with.
Thus my comment.
Like many have already stated, " if you want help, state the request clearly."

 

The less common abbreviations and acronyms don't mean much to those of us not familiar with the design of logic IC devices.

Oh, this is a standard well known acronym in electronics industry. I don't expect everyone knows about, but it is quiet well known.

Like many have already stated, " if you want help, state the request clearly."

I don't see "these many" here. Just you complaining about something you don't have knowledge about.

I think my post was quiety clear. If you cannot help because the topic is not familiar with you, simply don't answer, or investigate a bit more before. It is not correct asking for clarifications if you don't know anything about the topic, otherwise you are spamming the thread.
Not my fault if you don't know about it (not mean you should of course), but on a electronics HW forum with "Digital Design" and "IC Design" subforums, I think someone would have heard about UVM/Verification/System Verilog sometime...

Do I should explain what is FM and write a threatise on it if I open a thread about frequency modulation doubt? I don't think so.

 

@simozz,
MisterBill2 is a very helpful person.
Defence rests........

 

Oh, this is a standard well known acronym in electronics industry. I don't expect everyone knows about, but it is quiet well known.


I don't see "these many" here. Just you complaining about something you don't have knowledge about.

I think my post was quiety clear. If you cannot help because the topic is not familiar with you, simply don't answer, or investigate a bit more before. It is not correct asking for clarifications if you don't know anything about the topic, otherwise you are spamming the thread.
Not my fault if you don't know about it (not mean you should of course), but on a electronics HW forum with "Digital Design" and "IC Design" subforums, I think someone would have heard about UVM/Verification/System Verilog sometime...

Do I should explain what is FM and write a threatise on it if I open a thread about frequency modulation doubt? I don't think so.

The imperious attitude is a strong demotivator for anyone considering answering your request for help. It seems like you're at sea flying solo.

 

No problem for flying solo, I am used to it.
I am not the one spamming the thread. You added 0 value to the thread. Congrats.

I don't see requesting clarification with typical threads with HELP!!!! and weird schematics.
But that's it.

Thanks anyway.