using gates

Irving

Joined Jan 30, 2016
3,813
Here you have the output of an AND gate connected to the Q output of a JK FF. Not allowed!

Why use JK? & you cant leave JK inputs floating.

Where's the truth table or whatever that describes the functionality - impossible to decipher from schematic - so no way to validate.

Where are the gate designations, how do we differentiate them? " third gate down, fourth from left" doesn't work for me!

What are the devices with arrows and a floppy disc symbol?
 

Thread Starter

Livp

Joined Jul 1, 2022
12
i really dont know much of wht m doinng if thats a up down counter. i will try and make a simple one from of youtube
 

dl324

Joined Mar 30, 2015
16,732
i really dont know much of wht m doinng if thats a up down counter.
It turns out you're not being asked to count wins. You're supposed to implement the synchronizer; whatever that is.

The counter schematic I posted was to show you an example of not leaving so much space between symbols and not having unnecessary wire jogs and scenic routing. I don't usually put component designators on simulations because my simulator doesn't support that and people designing counters can usually follow the logic. I don't simplify the logic unless it's required.

Here's a CD4510 schematic from RCA:
1656859025322.png
The draftsperson who drew it favored using extra wire bends instead of spacing out the flip flops to avoid them.
 

MrAl

Joined Jun 17, 2014
11,280
It turns out you're not being asked to count wins. You're supposed to implement the synchronizer; whatever that is.

The counter schematic I posted was to show you an example of not leaving so much space between symbols and not having unnecessary wire jogs and scenic routing. I don't usually put component designators on simulations because my simulator doesn't support that and people designing counters can usually follow the logic. I don't simplify the logic unless it's required.

Here's a CD4510 schematic from RCA:
View attachment 270611
The draftsperson who drew it favored using extra wire bends instead of spacing out the flip flops to avoid them.
Hi,

It is interesting that you observed that the drawing was compacted horizontally. Looks like he was trying to save paper or something.
Even the last two lines on the right are folded in toward that last flip flop which does not make too much sense. Wondering if it was made with some automatic drawing method.

I like the fact that they included a CMOS protection network. Dont see that too often and it is important. They included a resistor too so whoever designed this had a good idea what they were working with.

After reading some posts here though i dont know exactly what is the goal of this project, exactly. That makes it hard to recommend something decent.
 
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