I started with a K-Map, which gave f(abc)=a'c + b'c
It also gave f'(abc) = a'c' + bc which is what I used to develop circuit since the outputs are active low.
(Note that this function is f-prime).
The rest of my thinking goes something like this (it's probably going to be hard to follow, but I'll give it a try):
Since we have like-logic in the terms (a & c both negated, and b & c both NOT negated), I figured this was the way to tackle the problem.
I started with "a NAND c" and found that the output was not the same for ALL of the desired inputs. In other words, an input of ab'c produced a "0" while the other terms (abc', ab'c', and a'b'c) all produced a "1".
So, I then tried "b NAND c" which produced a "1" for all the desired inputs. In addition, it produced a "1" for two other terms: a'b'c' and a'bc'. This became my first input A0.
These undesirable terms differ only in the b-term.
All I had to do then, was determine how I could disqualify those 2 terms without then disqualifying the desired terms. That is, I had to find a 2nd input that resulted in the same bit patterns for inputs a'b'c' and a'bc' but different for input a'b'c (which is a desired input).
Looking at the truth table, "c" is the only bit pattern that worked. But after looking at the bit patterns of "b NAND c" and "c" side-by-side, the only non-desirable input having the same bit pattern as any of the desired inputs was a'b'c' (the bit pattern is "10", which is shared by ab'c' and abc').
To eliminate that term, I did the same thing and found that input "a" did the job.
Note that desirable inputs result in one of the following outputs to go low:
Y3, Y5, or Y7
Similarly, the following outputs go low with undesirable inputs:
Y1, Y2, Y6
So, I could have connected my output NAND gate to those outputs instead. This would have given me f', so I would have needed to negate the output of that gate. Having only used two NAND gates, I could have used the 3rd as a NOT gate (by tying all of it's inputs together and connecting to the output).
Alternatively, I could keep my circuit as is, and negate the input to E1 and E2, which would allow me to tie it high, rather than low, as I did.
... there are several ways I could have incorporated that 3rd gate.
