# Using Demux and 3-input NAND

Discussion in 'Homework Help' started by freemind, Nov 3, 2010.

1. ### freemind Thread Starter New Member

Oct 17, 2010
4
0
How to implement, ab(c)'+a(b)'+a'b'c using 1-8 DEMUX(74138=decoder/demultiplexer) and 3 3-input NAND gates only.

Last edited: Nov 3, 2010
2. ### zgozvrm Active Member

Oct 24, 2009
115
2
Why not use only one 3-input NAND gate?

I guess you could hook up the other two as NOT gates, then double-negate the output...

3. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
Transform your function to a complemented product. The terms of the product will be the maxterms that you need to extract from your DEMUX and drive to the NAND gate. I don't see the need for more than one NAND gate.

4. ### zgozvrm Active Member

Oct 24, 2009
115
2
There is really no need to transform the function. If you check the data sheet on a 74138 decoder/demultiplexer, you'll see that the outputs are active LOW.

5. ### zgozvrm Active Member

Oct 24, 2009
115
2
EDIT:

I have to reconsider the problem. I just realized that I misread the function.

I thought we were dealing with abc' + ab'c + a'b'c

(note the "c" in the second term ... that wasn't given)

6. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
@ OP

Write down some boolean expressions and circuit estimations and post them so we can discuss further on them.

7. ### freemind Thread Starter New Member

Oct 17, 2010
4
0

can you please elaborate on this step "The terms of the product will be the maxterms".

Okay so what I get is that this function is equivalent to (a+b+c)(a+b'+c)(a+b'+c')(a'+b'+c'), it can be simplified but we don't need to simplify right?

it can be rewritten (a'b'c')'(a'bc')'(a'bc)'(abc)'. Don't really know what to do further.Thanks for your help.

8. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
We have:
f=abc'+ab'+a'b'c
=( (abc')' (ab')' (a'b'c)' )'
=( (a'+b'+c) (a'+b) (a+b+c') )'

We see now that the desired function is built from a NAND gate that combines the terms (a'+b'+c), (a'+b) and (a+b+c').
Thus, f=1 when one of these terms is 0. This happens when abc=110 or 10X or 001. You can take these signals from a 3-to-8 DEMUX. With inputs abc, the outputs 6,4,5 and 1 will be set to LOW for each of the above cases and can be used as inputs to the NAND gate.

However, this implementation requires one OR gate, which isn't available and can't be constructed from the two remaining NAND gates. Are you sure the initial expression isn't abc'+ab'c+a'b'c?

9. ### freemind Thread Starter New Member

Oct 17, 2010
4
0
No, pretty sure about the expression.
BTW here we have a 74138 IC, and you are using it as a decoder.
Thanks for help.

Last edited: Nov 4, 2010
10. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
I don't see any question mark here.

Does that mean you sorted everything out, and I can move to another thread?

11. ### zgozvrm Active Member

Oct 24, 2009
115
2
Since no body seems to be getting anywhere here, I'll post what I think is a valid solution (see attachment).

This solution only uses two NAND gates. If three are required, you should be able to figure it out from here (there are a few ways).

• ###### Logic Circuit.png
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12. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
Which is the MSB? A0 or A2?

13. ### zgozvrm Active Member

Oct 24, 2009
115
2
That's not really relevant here.

I set it up for the OP's equation:
abc' + ab' + a'b'c

So, MSB is "a", LSB is "c"

14. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
You got me wrong. What I asked about was wheather Y1 is activated for A2A1A0=001 or for A2A1A0=100. Since you havent referred to a specific IC it is not clear if the Select pins are sorted A2A1A0 or A0A1A2.

15. ### zgozvrm Active Member

Oct 24, 2009
115
2
Okay, gotcha!

It's a 74138 chip, as specified by the OP.

An input of A0 = 1, A1 = 0, A2=0 results in output Y1 = 0 (all others = 1)

16. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
Your circuit won't work. Here is the analysis of the output function:

F=(Y3Y5Y7)'
=( (A2'A1A0)' (A2A1'A0)' (A2A1A0)' )'
=A2'A1A0+A2A1'A0+A2A1A0
=c'a(bc)'+ca'(bc)'+ca(bc)'
=c'a(b'+c')+ca'(b'+c')+ca(b'+c')
=ac'+ab'c'+a'b'c+ab'c
=ac'+b'c

which is different from the required boolean function.

A correct circuit would be:

I couldn't meet the requirements though. I neede either two more NANDS or one OR or XOR (they are interchangeable in this case).

If anyone else has an idea on this, please stand up.

17. ### zgozvrm Active Member

Oct 24, 2009
115
2
Better look again!

Try comparing the truth tables for my function and the original ... they're the same!

18. ### zgozvrm Active Member

Oct 24, 2009
115
2
The original function:
abc' + ab' + a'b'c
= abc' + ab'(1) + a'b'c
= abc' + ab'(c' + c) + a'b'c
= abc' + ab'c' + ab'c + a'b'c
= ac'(b + b') + b'c(a + a')
= ac'(1) + b'c(1)
= ac' + b'c

19. ### zgozvrm Active Member

Oct 24, 2009
115
2
Ever heard of a Karnaugh map?

20. ### zgozvrm Active Member

Oct 24, 2009
115
2
Your circuit works correctly too, except for the fact that you used the OR gate (as you already pointed out). Also, you left G2B (pin 5) open; it should be grounded.