Hi, first post, hopefully it's a good one... I'm having an interesting problem trying to use a FET to turn off a QSPI device and was hoping someone else might have some thoughts/inputs.


Schematic here: http://imgur.com/a/vXbDj

When I toggle the N-channel FET low, the P-channel FET should open and one would expect the QSPI to turn off. This wasn't working, I was still seeing ~3.3V on the VCC pin. I added a 4K7 pull-down resistor between VCC and GND on the QSPI (not shown in the SCH). That had almost no effect on the circuit, when the N-channel FET was toggled low, the voltage at VCC was still ~2.9V... Out of view on the SCH are 4K7 external pull-up resistors on the HOLD and WP pins of the QSPI. The QSPI also has internal pull-up resistors on those same 2 pins. As far as I can tell, the only possible explanation is the pull-up resistors on those 2 pins are holding the VCC high. With this in mind, I replaced the 4K7 resistor with a 51R. This results in ~1.5V measured at VCC; the circuit can now switch off the QSPI, but it's not a very elegant solution.

I have not yet contacted Cypress, but it seems very unlikely the pull-up resistors inside the device are really that strong. They would have to be around 50OHM which seems crazy strong.

Does anyone have any other ideas?

If I were to re-design the circuit, I'd likely invert the output of the AND gate and just use the N-channel FET, remove the P-channel FET entirely. Thoughts?

Thanks for any and all help.


Mods Edit:
Please upload the schematic to the forum.

 

It's likely that the chip is being powered by signals on it's I/O lines.

Most I/O have input protection clamp diodes that clamp the pin to Vdd and Vss.
Unless all inputs are low, it's not going to be 'off'.

 

What is the purpose of R237 across the P-MOSFET?

I'm not sure what you mean by toggling the N-MOSFET "low" but when the N-MOSFET gate voltage is high and it is conducting so its drain voltage is near 0V, the P=MOSFET will also be ON and conducting.

 

What is the purpose of R237 across the P-MOSFET?

I'm not sure what you mean by toggling the N-MOSFET "low" but when the N-MOSFET gate voltage is high and it is conducting so its drain voltage is near 0V, the P=MOSFET will also be ON and conducting.

R237 is DNS - not installed

I'm aware of how the FETs work, I was just curious as to what others thought as to why the circuit isn't turning 'off'

 

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I'm aware of how the FETs work, I was just curious as to what others thought as to why the circuit isn't turning 'off'

If you know how they work then you should be able to determine why they are not working here.

What are both the MOSFETs' gate, drain, and source voltages when they are supposed to be off?

 

Clipped, BW image for the convenience of others:

 

If you know how they work then you should be able to determine why they are not working here.

What are both the MOSFETs' gate, drain, and source voltages when they are supposed to be off?

N-channel FET is working fine as expected. When the P-channel FET gate is 3.3V, the FET is not conducting, but I am still seeing ~3V on pin 8 of the QSPI device.

I believe this to be due to the pull-up resistors internal to that device, but when I add a 51ohm pull-down, the voltage is still ~1.5V. I believe the issue to be due to the P-channel FET not being a closure to GND, but was interested in what other thought.

 

When the P-channel FET gate is 3.3V, the FET is not conducting, but I am still seeing ~3V on pin 8 of the QSPI device.

If you are seeing 3V on pin 8 how do you know the FET is not conducting?
Are you sure the pinout of the P-MOSFET is correct with the source to the 3.3V?
If you interchange the drain and source, the FET will conduct through its substrate diode even when off.

 

Yea, I verified the pinout as that's what I thought was wrong at first as well...

 

I agree with Sensacell. If the chip is in standby, the typical current draw is 70uA, (figure from datasheet) which can be given by the IO signals whichever is high, through the protection diodes clamped to Vcc.

This can be checked out - Turn Reset, WP, HOLD all Low, just to put the device against inadvertant flash corruption, and turn the other IO Lines Low and then turn off Vcc by turning off P Channel MOSFET.

 

Did you resolve this? It would be nice to offer closure to any of the casual readers of this forum.

 

Did you resolve this? It would be nice to offer closure to any of the casual readers of this forum.

Unfortunately, no.

I replaced the AND gate with a NAND gate and removed the P-channel FET from the circuit, but this also didn't work. I had the opposite problem, I could not get the memory device to turn on.

I think the only way to truly correct this would be to use 2 FETS in a push-pull configuration.

 

Just to clarify, when I removed the P-channel FET, I obviously jumped the GATE to the DRAIN on the P-channel FET pads.

 

Just to clarify, when I removed the P-channel FET, I obviously jumped the GATE to the DRAIN on the P-channel FET pads.

Have you tried disconnecting the data lines yet, or forcing them low, as others have suggested? This sounds exactly like a problem I had with an LED driver chip which would remain powered up through the clamping diodes on the data lines. I strongly suspect the data lines are your problem.

 

If the control signal there is no any problem then you can try the modified circuit below.
You can use any small signal bjt for Q1 and any Ic current exceed 300 mA for Q2.

If you know the draw current for U26 ic then you can increasing the 82Ω to match what you want.