Your assignment is to do a paper design of an octal-to-7-segment common cathode decoder for digits 2, 3, 4, 5, 6 and 7 using the least possible number of NAND gates. You are to assume that only these octal digits are applied to the inputs of the decoder, i.e. combinations for digits 1 and 7 are never applied. Your solutions must show all the design steps taken, i.e. a description of the task, requirements definition, design approaches such as truth-table(s), simplification using K-maps or Boolean theorems, and the implementation (circuit diagrams) using standard logic symbols. Use a Truth-table format as shown below.

 

 

Start by drawing the truth table.

 

Start by drawing the truth table.

I have already draw the truth table and the kmap. I am not sure if my kmap is correct and after that I am not sure what to do.

 

I have already draw the truth table and the kmap. I am not sure if my kmap is correct and after that I am not sure what to do.

How do you expect anyone to be able to help you if you don't show us your work?

 

It seems odd, but for some strange reason, newbies here seem to think we have a crystal ball that knows what they have already done, and they don't need to show it.
And that we will then do their homework for them.

 

It seems odd, but for some strange reason, newbies here seem to think we have a crystal ball that knows what they have already done, and they don't need to show it.
And that we will then do their homework for them.

You mean, similarly to this:

sir/madam
i am designing a switching amplifier with DC input voltage of 200V to supply current of max 100A to dc motors and i am using IGBT in it can you please tell me about any IGBT which can satisfy my requirements.


Thanking you

 

Your assignment is to do a paper design of an octal-to-7-segment common cathode decoder for digits 2, 3, 4, 5, 6 and 7 using the least possible number of NAND gates. You are to assume that only these octal digits are applied to the inputs of the decoder, i.e. combinations for digits 1 and 7 are never applied.

You should post the complete text for the problem.

You say it should decode 2-7 but 1 and 7 are invalid counts, so that means display 2-6. What about zero?

ff the requirement is to display 2-6 with 0,1,7 invalid counts, I did it with 10 gates.

I'll show my truth table, kmaps, and simplifications after you've solved the problem.

 

The instructions appear to have an conflicting error - "decoder for digits 2, 3, 4, 5, 6 and 7" but "combinations for digits 1 and 7 are never applied".

As stated, a 7 is to be decoded even though it is never applied, and behaviour for a 0 is undefined.

Surely it should be that digits 1 and 0 are never applied, or that the decoder handles 0,2,3,4,5,6.

 

I have to do the number 2-7.
0 and 1 don care

 

I have to do the number 2-7.
0 and 1 don care

I could see handling 7 even if it wasn't ever used if it simplified the logic, but it doesn't.

 

I could see handling 7 even if it wasn't ever used if it simplified the logic, but it doesn't.

I don’t understand

 

I don’t understand

The logic is simpler if 0, 1, and 7 are treated as don't cares. Your instructor already made you jump through hoops by requiring you to only use NAND gates. Is your instructor a sadist?

 

The logic is simpler if 0, 1, and 7 are treated as don't cares. Your instructor already made you jump through hoops by requiring you to only use NAND gates. Is your instructor a sadist?

My assignment is to do a paper design of an octal-to-7-segment common cathode decoder for digits
2, 3, 4, 5,6 and 7 using the least possible number of NAND gates….
I have to draw truth table, kmap, Boolean theorem and do this circuit in multisms

 

My assignment is to do a paper design of an octal-to-7-segment common cathode decoder for digits
2, 3, 4, 5,6 and 7 using the least possible number of NAND gates….
I have to draw truth table, kmap, Boolean theorem and do this circuit in multisms

Fine. We're not going to do your homework for you. Show us your work and tell us when your assignment is due.

Doing a paper design and simulating in Multisim seems like a contradiction to me... Not sure you or your instructor know what you're doing.

 

The logic is simpler if 0, 1, and 7 are treated as don't cares. Your instructor already made you jump through hoops by requiring you to only use NAND gates. Is your instructor a sadist?

And for the multisim template I have attached on top

 

You seem to not be grasping a very key point -- we will NOT do your homework for you. You have to show your best attempt to solve the problem and describe where/how you are getting stuck. We can then look at your work and guide you toward getting past your present difficulty. We cannot do that if you won't show your work.

 

You seem to not be grasping a very key point -- we will NOT do your homework for you. You have to show your best attempt to solve the problem and describe where/how you are getting stuck. We can then look at your work and guide you toward getting past your present difficulty. We cannot do that if you won't show your work.

 

That is my truth table and kmap. I am not sure what to do afterwards. I must find the Boolean expression