Hi,
I am trying to design a counter that counts to 999. It counts up when one button is pressed and down when another button is pressed.

I have integrated three 4510B counter chips and their decoders connected to seven segment displays, with monostables to change the up/down count connection and maintain its change for a long enough amount of time to send a count pulse within it.

This all works but when i switch on the circuit, the bottom two counters (tens and hundreds) start on nine. Also, after pressing the reset and beginning to count, the counters carry out one pulse to early, so the counter goes from 9 to 19 to 10 to 11.

Any ideas what I have done wrong or how to fix this?

Screenshots of the circuit and waveform attached:

 

That is what happens when the counters are wired asynchronously.
Wire them as synchronously counters.

 

Oh ok, I have read about the difference but is there a connection difference that I need to make to change them to synchronous counters?
Thanks

 

Connect the CLOCK inputs together to the same source.
Connect CARRY OUT of the 1st stage to the CARRY IN of the 2nd stage.

 

It might be that the counters are not powering up with all zeros. Your schematic does not show the pull-down resistor on the reset line. You can add a power-on reset by placing a small capacitor across sw3.

ak

 

Oh ok, I have read about the difference but is there a connection difference that I need to make to change them to synchronous counters?

It's in the datasheet:

 

So I attempted to attach them as synchronous counters and the segments now all starts at zero.The issue is they do not carry out at all. Neither the tens nor the hundreds change when the units go past nine back to zero to start again.

Various sites and the data sheet contradicted on weather to integrate the OR Gate or not, but is hasnt made any difference to the circuit function. I will attach schematics for it with and without the OR gate:

 

Neither schematic has a pull-down resistor on the Reset input. This might not be a critical error in simulation, but an assembled circuiit will not be stable.

For the lower schematic there should be two OR gates.

Note, the Carry Out signal is negative-true; the 4510 symbol should have a bubble. Without it the schematic is hard to interpret correctly.

ak

 

Since the Q1 operates on a low frequency then the R26 can be use as 10K.

 

Various sites and the data sheet contradicted on weather to integrate the OR Gate or not, but is hasnt made any difference to the circuit function.

An OR gate isn't required to cascade those counters.

The issue is they do not carry out at all. Neither the tens nor the hundreds change when the units go past nine back to zero to start again.

Don't see anything wrong in the wiring. Advance the clock to 9 and stop the counters. Check carry out from the first counter to see if it's LOW.


It would be helpful if you developed some "style" to make your schematics easier to read. Avoid scenic wire routes.

This is for CD4029 which is similar to CD4510, except it doesn't have a reset:


I "violated" the "left-to-right rule" because it made sense for this circuit.