Unused inputs question

Thread Starter

metermannd

Joined Oct 25, 2020
80
I know, I know, this has been discussed on many a thread, and I did peruse a few a few minutes earlier, but didn't quite find the answer I was after, especially looking at the original version of the circuit I'm working on.

It seems the rules of thumb are that unused inputs on TTL gates should be pulled up... applicable to buffer ICs as well?

One circuit I'm working on replicating uses only half a 74LS241. The unused half has BOTH the inputs AND outputs left floating (pins 3-5-7-9-11-13-15-17), with the control line (19) pulled up to 5V through a 1K resistor.

Should I go back and modify the circuit to ground pins 11-13-15-17? (the original circuit was developed and produced around 1982)
 

djsfantasi

Joined Apr 11, 2010
7,187
I know, I know, this has been discussed on many a thread, and I did peruse a few a few minutes earlier, but didn't quite find the answer I was after, especially looking at the original version of the circuit I'm working on.

It seems the rules of thumb are that unused inputs on TTL gates should be pulled up... applicable to buffer ICs as well?

One circuit I'm working on replicating uses only half a 74LS241. The unused half has BOTH the inputs AND outputs left floating (pins 3-5-7-9-11-13-15-17), with the control line (19) pulled up to 5V through a 1K resistor.

Should I go back and modify the circuit to ground pins 11-13-15-17? (the original circuit was developed and produced around 1982)
Don’t ground the outputs. You might create a short circuit damaging the chip.

Original TTL design floating inputs were treated as high signals. You could get away without pulling them up or down (unless you needed a low input for some reason)

CMOS is different. All unused inputs must be tied either high or low else the chip will be unstable
 

dl324

Joined Mar 30, 2015
12,210
Should I go back and modify the circuit to ground pins 11-13-15-17? (the original circuit was developed and produced around 1982)
I would if I was going have my name associated with a design. I leave all sorts of inputs floating when I'm prototyping circuits, but I always tie off inputs if it moves past that stage.
 

crutschow

Joined Mar 14, 2008
25,980
It seems the rules of thumb are that unused inputs on TTL gates should be pulled up... applicable to buffer ICs as well?
They can be left floating if they have no effect on your circuit operation.
Otherwise they are normally pulled high through a resistor since the input current is negligible when high, so it draws a little less power than when the input is low, which requires sinking some current to ground.
 

MrChips

Joined Oct 2, 2009
22,468
Pull up or pull down, that is the question.
There is no rule of thumb. You have to look at the effect on the input.
Pull up if it needs logic high.
Pull down if it needs logic low.
Never leave the input floating.
Outputs need no pull up or pull down.

If is 7400 series TTL (not CMOS 74C, 74AC, 74ACT, 74HC, 74HCT, 74LVC) and the input is not needed and has no effect on the circuit then you can leave it alone.
 

Thread Starter

metermannd

Joined Oct 25, 2020
80
Since I'm working with 74LS, I'll just stick with the original design and leave them floating.

It would be nice if there was a 4-channel version of the 74LS241, as it seems a waste to be using only 3 of the 8 buffers in the first place.

Likewise, I'm using a 74LS375 quad latch, and that one is only using a single latch. Couldn't I get by with a 7474 or similar?
The input is the main 1MHz clock, and the output goes to the clock pin of the 8279.
 

AnalogKid

Joined Aug 1, 2013
8,804
I disagree with the comments saying it is OK to leave unused TTL inputs floating. Yes, circuit analysis indicates that a floating input will be "seen" as a logic high or 1, but it also will act as a radio antenna, and will respond to things like the motor start relay in your refrigerator. Tying unused inputs high or low *always* is better than letting them float.

ak
 

MrChips

Joined Oct 2, 2009
22,468
TS is using circuits with unused sections.
For example, suppose one gate in a 74LS00 IC is not used, then it is ok to leave the input and output pins not connected.
This is only true for BJT logic and not CMOS logic.

1608820389187.png

"TTL" BJT inputs are relatively low impedance inputs and are inherently pulled up through R1 and the base emitter junction of the input transistor Q1.

1608820977694.png
 

AnalogKid

Joined Aug 1, 2013
8,804
TS is using circuits with unused sections.
For example, suppose one gate in a 74LS00 IC is not used, then it is ok to leave the input and output pins not connected.
Understand. Don't care. No, it's not.

I do not want to hijack this thread with a contentious discussion of situational consequences. But ...

What we learn when we are young stays with us forever, and no amount of later training and experience completely erases it. This is the kind of thing that makes Mars probes and 737's fall out of the sky.

https://www.latimes.com/archives/la-xpm-1999-oct-01-mn-17288-story.html

ak
 

MrChips

Joined Oct 2, 2009
22,468
True. But it depends on if you are designing a Mars Rover or a controller for your kid's go-cart.
You may omit the 0.1μF power supply decoupling capacitor in the latter but not when you are a professional on the job.
Please, let's keep things in its proper context.

Off topic: We had a standing procedure/joke in our research lab that an instrument was not a finished build if you couldn't find a place to use 5-minute epoxy and masking tape or duct tape.
 

AnalogKid

Joined Aug 1, 2013
8,804
True. But it depends on if you are designing a Mars Rover or a controller for your kid's go-cart.
You may omit the 0.1μF power supply decoupling capacitor in the latter but not when you are a professional on the job.
And that is exactly the opposite of my point. It should it not matter. Good design practices are not situational, and ***teaching*** that they are is a critical failure.

ak
 

Thread Starter

metermannd

Joined Oct 25, 2020
80
Would the presence of a ground plane on the PC board and a decoupling cap associated with the ICs in question mitigate this 'antenna' tendency?
 

MrChips

Joined Oct 2, 2009
22,468
Would the presence of a ground plane on the PC board and a decoupling cap associated with the ICs in question mitigate this 'antenna' tendency?
I am not opposed to what AK is preaching.
I make a point of telling my students this personal story.

I was scheduled to go under a CyberKnife to treat a brain tumor. On the day of the procedure I googled CyberKnife. I discovered that the high energy x-ray machine was mounted and manipulated by a robotic arm manufactured by a leading robotics engineering company. As it turned, I had worked on the R & D in developing both the software and hardware for the arm. The lesson is, if you are going to do a job, do it right because you never know when it might come back to bite you.

So to answer your question, it is better to deal with the issue rather than find secondary or tertiary ways of mitigating the problem. If a floating input can potentially cause a problem then don't allow it to float.

Will a floating input on an unused gate, flip-flop, or bus driver cause a problem?
Whereas a floating CLR, LOAD, PRESET or RESET pin on a counter or flip-flop being used is likely to be a problem.

In another vein, leaving inputs floating on analog circuits such as opamps and comparator chips is a bad idea because they can cause unwanted oscillations and increased power consumption.
 

Thread Starter

metermannd

Joined Oct 25, 2020
80
After mulling it over, considering the original design and its usage, and my efforts at design 'best practices' otherwise, I will leave the unused inputs on the 74LS241 (and the 74LS368 section I repurposed) as is. That's on me.

It IS good to know the 'why' of certain best practices, however.
 
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