Hi,
I am new in circuit design. I use a shift register with Hall sensor as switches.
I use only 2 inputs of the shift register (type: CD4021 parallel In). with the switches and pull up resistors.
I would like to have definded state for all unused 6 inputs. So I will connect them over pull up to 5 volt.
Do I have to use one pull up resisitor per input. Or can have one pull up resistor for all inputs (I have less place in my circuit)
Thank you for answer.

 

One pull-up for all unused inputs should do the job.

 

Hi,
I am new in circuit design. I use a shift register with Hall sensor as switches.
I use only 2 inputs of the shift register (type: CD4021 parallel In). with the switches and pull up resistors.
I would like to have definded state for all unused 6 inputs. So I will connect them over pull up to 5 volt.
Do I have to use one pull up resisitor per input. Or can have one pull up resistor for all inputs (I have less place in my circuit)
Thank you for answer.

I would've thought no resistor was needed at all. Aren't the shift register inputs very high impedance, meaning there will be negligible current through them, even without a resistor? What purpose does the resistor serve?

 

One pull-up for all unused inputs should do the job.

Than you for soon answer.
Would you please explain me why dose it works. Jus for learning.
Or betther how dose it works. Is there not a iteration ask for each input

 

The resistor is a hold-over from the bipolar days before CMOS. I have not used pull-up resistors on unused CMOS inputs since CMOS SSI parts first became available and have not experienced any problems and that includes products in production.

 

The resistor is a hold-over from the bipolar days before CMOS. I have not used pull-up resistors on unused CMOS inputs since CMOS SSI parts first became available and have not experienced any problems and that includes products in production.

Thank you for reply.
Is there a disadvantage for allready used resistors (specially for used inputs). I would not like to change all the circuit.

 

There were articles written recommending the use of pull-up resistors on unused inputs on TTL gates.
I have not seen similar recommendations for pull-up resistors on unused inputs on CMOS gates.

In both cases, TTL and CMOS, unused inputs must not be left "floating". The issue is more severe with CMOS gates.

The input resistance of CMOS gates is very high, in excess of 1MΩ. An unused input becomes an antenna for stray electrostatic and electromagnetic fields. This could bias the input to logic low or logic high, or even worse, into the linear region between logic low and logic high.
When a CMOS input is biased in the linear region, the gate supply current increases dramatically and can cause unexpected behaviour in the operation of the integrated circuit.

 

Thank you for reply.
Is there a disadvantage for already used resistors (specially for used inputs). I would not like to change all the circuit.

As long as the pull-up resistor is 1MΩ or less you would be ok.
If a single pull-up resistor is used multiple inputs, reduce the pull-up resistor to 100kΩ or lower.

Just remind yourself that you can buy resistors of 0Ω.

 

Than you for soon answer.
Would you please explain me why dose it works. Jus for learning.
Or betther how dose it works. Is there not a iteration ask for each input

A single resistor works because all you are trying to do is establish a valid logic level (HI in this case) at the inputs. You just need to know what the maximum current that an input might need when it is being driven HI. In the case of 74HC CMOS, the maximum input leakage specified is 1 μA. If you are powering from 5 V and your supply is at the minimum of 4.5 V, then the minimum voltage at an input that is guaranteed to still be recognized as a HI is 3.15 V. That means that you can drop at most 1.35 V while letting a current of 1 μA through, which corresponds to minimum of 741 kΩ. So a 1 MΩ should work for a single input. But since the leakage current is almost independent of the value of the pullup resistor (since the voltage on the gate is going to be in the same ballpark), there is little reason no to use something smaller. I tend to use 100 kΩ or 10 kΩ, depending on what I have handy. For designs I expect to be around awhile, I use 100 kΩ.

If you are using the same resistor to pull multiple inputs HI, then you need to allow for each input having the max leakage current. The easiest way is to just take your single-input pullup value and divide by the number of inputs it is servicing. Using a 100 kΩ pullup allows you to handle 10 inputs.

Hopefully you can see how I did this so that you can do a similar calculation, if you need/want to, for whatever family you are using. Also, you do something similar if you are designing a pull down.

But on CMOS parts, you can tie them directly to the power rails. The advantage of using a pullup (or pulldown) resistor is that you are able to overdrive the signal and force it to go low, which may aid in troubleshooting a circuit. But to do that, you need to use a separate resistor for each unused input (unless there are groups of inputs that you know you will always want to be at the same level).

I have no idea what you mean by an "iteration ask". Could you please clarify?

 

When a CMOS input is biased in the linear region, the gate supply current increases dramatically...........

Don't think you meant that.
It's the input stage complementary MOSFETs' drain-source current from the power supply that increases.

 

Don't think you meant that.
It's the input stage complementary MOSFETs' drain-source current from the power supply that increases.

By "gate" I meant a logic gate and not the gate of a FET or MOSFET structure.
I realized the potential confusion when I wrote this but I let it go anyway. At least one person caught the confusion.

However, if the input stage is biased in the linear region I would assume that all stages following would also be biased in the linear region.

 

However, if the input stage is biased in the linear region I would assume that all stages following would also be biased in the linear region.

Possible, but unlikely. The width of the linear region is actually pretty narrow, but floating gates seem to seek it out. The follow on stages, however, are not floating, but rather being driven at a poorly defined level. But while that level is likely outside of the defined logic thresholds, it is probably not within the much narrower region at which shoot-through occurs. As the supply voltage decreases, however, the likelihood of cascading shoot-though increases.