Hello, In the attached LTSPICE i am trying to simulate the level shifter shown below.
I see many components but i don't know what is crucial .at first i put 20p but the signal get distorted as shown below.
Then when i tried to simulate 1uF (as in the attached file) it got much better.
What is the functionality of these circuit? how the circuit elements play together?
What is the role of the different elements in the level shifter?
Thanks.

 

Your question is missing some important details. In the first schematic,

Which circuit point is the input?
Which circuit point is the output?
What is the input driving voltage range?
What is the desired output voltage range?

Also, the left side of the LTS image is cut off, so we can't see the voltage values.

ak

 

Hello Analog kid , LTSpice file was attached .
Regarding your questions :
1. Point A is the input
2.point B is the output
3.input pulse is 3.3-0 120ns wide .
Desired output is the input pulse with the reduced by 1V(for example )
When I put 20p capacitor then the signal was not square but with a slope as shown in the photo.
What is the role of the different components presented in the white schematics for good level shift ?
Thanks .

 

Desired output is the input pulse with the reduced by 1V(for example )

All you need is a voltage divider for that.

 

Simply reducing the output voltage from +3.3 V to +2.3 V might be as simple as two resistors forming a voltage divider. However the output impedance might be too high to drive whatever the downstream component or circuit is.

I think the first schematic in #1 is intended for a 5 V signal, because the 3.6 V zener diode means that the output will not change state with a 3.3 V input. It will sit at -2.5 V, pulled there by R16 and R18 in series. With a 5 V signal, the output positive peak would be +1.4 V, and the negative peak would be -2.5 V.

Again, what is the desired output voltage range. "reduced by 1 V" is not at all helpful. Do you want the signal to be DC level shifted by -1 V? Do you want the peak-to-peak amplitude reduced by 1 V? IOW -

What are the desired output positive and negative peak voltages?

ak

 

In your LTS schematic, D1 is shown as a Shottkey diode, not a zener diode. It does not conduct, which is why the output returns to -2.5 V no matter which state the input is in. The circuit is basically a simple R-C differentiator.

ak

 

Hello ,its propably for some reason a differentiator.in my point of view when Vi-Vout>Vbreak_down of zenner then the Zenner will open_up and make Vi=Vout.
but why exactly the zenner does offset drop? what is the analog machanism to that?
Thanks.

 

If it is continuously reverse-biased and conducting, a zener diode is an adder. It adds (or subtracts, depending on circuit polarities) a fixed DC value to the signal it is influencing. A 1N750 is a 4.7 V zener diode, and the circuit in #7 spans 5.8 V, so the zener diode is conducting only when the input 3.3 V signal is high. At that time, the D1 anode is 4.7 V less than the D1 cathode.

Disconnect one end of C1 to see the zener diode action. You also can see the current through D1, and see that it goes to zero when tot total voltage across it is less than 4.7 V.

ak

 

Hello Analogkid ,There is a very good advice you said.I could do just a voltage divider to do level shift.
The next level is shown below described after point B.
how do i know that the impedance on the left of point B equals the impedance to the right of point B.
How analog designers plan the impedance matching between the sections?
Thanks.

"However the output impedance might be too high to drive whatever the downstream component or circuit is."

 

Matching impedance is needed only in very specific circumstances. In most cases, we want the input impedance to be much higher than the output impedance. A factor of 10 is a good rule of thumb, higher is even better. For example, a speaker might be 4 Ohms, but the output impedance of the amplifier should be a fraction of an Ohm for best results.

When using a voltage divider, determine how much current is required by the input, and make the current in the divider at least 10 times higher. Digital logic input currents are often stated in nanoamps, we are not talking about a lot of current here.

For CMOS logic, resistors in the range of 10K to 100K are typical.

 

What is that schematic from? What does the overall circuit do? It is drawn in an unconventional manner, making it difficult to decipher. The Q2 stage looks like a saturated switch, pulling the R17 resistor string, and the signal at CJ13, up from -8V -ish to GND. I say -ish because there is a DC path from through the Q1 base-emitter junction.

The Q2 stage is a significant load on point B, and adds one base-emitter voltage drop to the circuit. Now the input at A must be even higher to cause Q2 to turn off.

ak

 

Hello Analogkid, the full circuit is as shown below.
I know that we enter a pulse to it.
from A to B i guess its a level shifter ,then from B to C its a buffer,from C to D its a darlington.
What do you think is the general logic of these stage.
what is the purpose in your opinion?
Thanks.

 

Hello,I got a photos of testing this circuit.
the green signal is the signal we what to look at.
Photo with B it means the signal at point B.
Photo with C it means the signal at point C.
So it is an interter but it also amplified the signal.

I know the stage at point C is common emitter with PNP transistor.correct?
i have R19 R22 C23.
what is the important component surounding the common emitter i need to pay attention to in my simulation?

Thanks.