Undefined Voltage Region in Switching Digital Logic

Thread Starter

Vinnie90

Joined Jul 7, 2016
78
Hi all,

I'm trying to figure out the behavior of a XOR logic gate during its switching. I have selected this (http://www.ti.com/lit/ds/symlink/sn74ahc1g86.pdf) XOR gate for my project. I read in the datasheet that VIH = 2.1V and VIL = 0.9V (@vdd = 3V). I know I'm not supposed to operate statically this device in the undefined voltage region (between 0.9V and 2.1V) but what happens during the switching of one input?

I have one of the inputs with a fast falling time (~100ns) while the other is supposed to be slower (coming from an RC discharge). What happens to the output when one of the input is @0V while the other transitions from 3.3V to 0V (it takes some hundreds of us to transition from 2.1V to 0.9V)?
 

Papabravo

Joined Feb 24, 2006
12,405
Hi all,

I'm trying to figure out the behavior of a XOR logic gate during its switching. I have selected this (http://www.ti.com/lit/ds/symlink/sn74ahc1g86.pdf) XOR gate for my project. I read in the datasheet that VIH = 2.1V and VIL = 0.9V (@vdd = 3V). I know I'm not supposed to operate statically this device in the undefined voltage region (between 0.9V and 2.1V) but what happens during the switching of one input?

I have one of the inputs with a fast falling time (~100ns) while the other is supposed to be slower (coming from an RC discharge). What happens to the output when one of the input is @0V while the other transitions from 3.3V to 0V (it takes some hundreds of us to transition from 2.1V to 0.9V)?
In that region a CMOS gate may operate linearly with an associated power dissipation that may exceed the device's capability. You are essentially placing a low impedance load across the power supply. Buffer the RC signal with a Schmitt Trigger device, unless you enjoy huffing the fumes from burning plastic.

https://en.wikipedia.org/wiki/Schmitt_trigger
 

crutschow

Joined Mar 14, 2008
23,347
What happens to the output when one of the input is @0V while the other transitions from 3.3V to 0V (it takes some hundreds of us to transition from 2.1V to 0.9V)?
It can oscillate or otherwise act erratically.
Besides using a Schmitt-trigger buffer at the slow input as PB suggested, another solution is to make an XOR gate with Schmitt trigger NAND gates, which have a sharp output transition even with a slow moving signal for either input.
input.
Circuit below:
upload_2019-10-8_13-59-44.png
 

Thread Starter

Vinnie90

Joined Jul 7, 2016
78
Got it! So one usually used in switching logics it is not a problem because of fast rising and falling edge? I was thinking of using a comparator to sharpen the edge and set the switching voltage around 0.6V.

Thanks for the explanation
 

WBahn

Joined Mar 31, 2012
24,693
Got it! So one usually used in switching logics it is not a problem because of fast rising and falling edge? I was thinking of using a comparator to sharpen the edge and set the switching voltage around 0.6V.

Thanks for the explanation
A logic gate essentially is a comparator, so if your signal is changing slowly enough to present a problem for a standard logic gate, then you may see the same problems with a normal comparator. The problem is that as you get close to the switching threshold, things are changing slightly inside the chip which might move the switching threshold in the same direction, resulting in the comparator switching back, which moves the threshold back to where it was causing the comparator to switch again. This flailing continues until the signal has moved far enough away from the threshold to keep the noise in the threshold from having an effect. What a Schmitt-trigger does is forcefully moves the threshold in the opposite direction of the changing input so that a large gap between signal and threshold appears as soon as the comparator first changes.
 

Thread Starter

Vinnie90

Joined Jul 7, 2016
78
@WBahn hold on...I understand what @Papabravo is saying about the gates operation (what I have in mind is something similar to the pmos and nmos both conducting as in a inverting gate). What you are claiming here is something about the hysteresis of the gate, correct?

When I use a comparator don't I have just a hard threshold that can oscillate back and forth (when used without hysteresis) because of the noise?
 

crutschow

Joined Mar 14, 2008
23,347
So, in summary, you need a circuit with hysteresis (however it's designed) for the slow-moving input.
 

WBahn

Joined Mar 31, 2012
24,693
@WBahn hold on...I understand what @Papabravo is saying about the gates operation (what I have in mind is something similar to the pmos and nmos both conducting as in a inverting gate). What you are claiming here is something about the hysteresis of the gate, correct?

When I use a comparator don't I have just a hard threshold that can oscillate back and forth (when used without hysteresis) because of the noise?
And if that "hard" threshold moves back and forth the wrong way because of the noise, you've turned your comparator into an oscillator for signals that stay too close to the threshold.
 

Thread Starter

Vinnie90

Joined Jul 7, 2016
78
Hi all,

thanks for all the answers. Let me recollect all the thoughts until now:
- Question: the original question was about the behavior in the undetermined input region for logic gates (I am trying to calculate more or less the discharging time of a capacitor to make a capacitance meter). The question was what will be the output for a slow transition high to low

Answers
- @Papabravo: within the undefined region the transistors are not fully in saturations, thus there is some ground bounce (current flowing from supply to gnd with low impedance) that can damage the gate -> Transitions have to be reasonably fast to reduce the power.
-@WBahn and @crutschow: the undefined region comes from the hysteresis of the input stage in the logic gate to avoid unwanted transitions due to noise on the input. Use of a schmitt trigger -> Also get rid of the slow falling edge
-@danadak: for sequential logic systems there can be troubles because of the propagation delay and hold times. The output does not behaves correctly when the all states of the state machine are not univocally determined.

If I understand correctly however, the hysteresis and undefined regions are different things. In fact, to have a robust noise rejection a couple of hundreds millivolts should be sufficient, while undetermined regions can be in the order of Volts (depending on the logic family).

Following all you advices I have added before my XOR logic gate a voltage comparator with some hysteresis (lt6700) to sharpen the falling edge of the RC section and avoid a very slow transition at the input of the logic gate.
 

Attachments

WBahn

Joined Mar 31, 2012
24,693
Hi all,

thanks for all the answers. Let me recollect all the thoughts until now:
- Question: the original question was about the behavior in the undetermined input region for logic gates (I am trying to calculate more or less the discharging time of a capacitor to make a capacitance meter). The question was what will be the output for a slow transition high to low

Answers
- @Papabravo: within the undefined region the transistors are not fully in saturations, thus there is some ground bounce (current flowing from supply to gnd with low impedance) that can damage the gate -> Transitions have to be reasonably fast to reduce the power.
-@WBahn and @crutschow: the undefined region comes from the hysteresis of the input stage in the logic gate to avoid unwanted transitions due to noise on the input. Use of a schmitt trigger -> Also get rid of the slow falling edge
-@danadak: for sequential logic systems there can be troubles because of the propagation delay and hold times. The output does not behaves correctly when the all states of the state machine are not univocally determined.

If I understand correctly however, the hysteresis and undefined regions are different things. In fact, to have a robust noise rejection a couple of hundreds millivolts should be sufficient, while undetermined regions can be in the order of Volts (depending on the logic family).

Following all you advices I have added before my XOR logic gate a voltage comparator with some hysteresis (lt6700) to sharpen the falling edge of the RC section and avoid a very slow transition at the input of the logic gate.
The undefined region comes from a number of factors. Let's review what the defined regions mean.

VinLOmax is the highest input voltage that the gate is guaranteed to recognize as a logic LO.
VinHImin is the lowest input voltage that the gate is guaranteed to recognize as a logic HI.

For MOST of the voltages between VinLOmax and VinHImin, the gate will recognize it as one or the other and will operate perfectly fine, but the part manufacturer is not guaranteeing which state that voltage will be recognized as. The actual limits are a function of many things, including temperature, production tolerances, supply voltage, and device mismatch.

There is a much narrower region, somewhere between VinLOmax and VinHImin, where the behavior of the device CAN become problematic. It MAY result in large shoot-through currents if both the pullup and pulldown networks are asserted at the same time. It MAY oscillate while the input voltage stays within that region.

IF there is hysteresis in the input stage (of a typical logic gate or comparator) it is NOT there intentionally. IF it happens to be hysteresis in the normal sense (the threshold moving in the direction opposite the changing input), then the device will be less likely to oscillate near the threshold. IF it happens to be in the other sense (the threshold moving in the same direction as the changing input), then the device will be more likely to oscillate near the threshold. In either case there may or may not be large shoot-through currents; these are largely unrelated phenomena.
 
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