Unable to read back registers via SPI on the ENC28J60 Ethernet chip

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Samyukta Ramnath

Joined May 21, 2015

I am using a CC1352P1 Launchpad from TI to connect with an ENC28J60 SPI-Ethernet bridge chip. I wanted to confirm first that I am able to get a response from the ENC28J60, so I tried to write to a register and read back the value I just wrote to that register. I am using a 4MHz SPI clock from the CC1352P1 master, with a polarity of 0 and a phase of 0.

For example, I wrote a value of 0b10101010 to the ERXSTL register at address 0x08 in the first bank. To do this, I wrote the value 0b 010 01000 10101010 or 0b01001000 10101010. I first sent in the byte with value 72 (or 0b01001000) and then sent in the byte with value 170 (0b10101010). I can see the SPI clock coming out of the CC1352P1, set at 4MHz, and I can see the Chip select from the CC1352P1 master go low during each byte transfer on my oscilloscope. I can also see the values that I am writing go out MSB first (namely, 0b01001000 and 0b10101010) on the MOSI line my oscilloscope. Then, when I try to read back this same register, I send the instruction 0b 000 01000 00000000 or 0b 00001000 00000000 or 0x08 as the first byte and 0x00 as the second byte. I am checking the MISO line on my oscilloscope, and I always see the last bit go high, every other bit is always low.

I tried also to read back the EREVID register by first setting the BSEL1 and BSEL0 bits to 11 to select the third bank, then reading from address 0x12 by sending in the following two bytes : 0b 000 10010 0000 0000 or first byte 0x12, second byte 0x00. I always get back 0x01, on the MISO line.

I tried setting the PHLCON register to get the LEDs to blink as well, by first writing the address of PHLCON (0x14) into the MIREGADR register, then writing the value 172 to write into MIWRL, then sending 59 into the higher 8 bits to write into MIWRH register. I did not get any response.

I am sure that the SPI communication on the CC1352P1 works since I have tested it with two CC1352P1 boards, one as a master and one as a slave, and I am also seeing the SPI clock generated and seeing the chip select go low when a byte is being transferred. Please help me out with what might be going wrong.

I am also not able to see any signal on the OSC1 or OSC2 pins on the chip, but I'm able to see a 6.25 MHz CLKOUT signal from the chip.

Warm regards,


Joined Nov 10, 2018
I can see the Chip select from the CC1352P1 master go low during each byte transfer
I think this is what's wrong. The ENC28J60 expects /CS to stay low during the entire transaction. [Ref data sheet (#39662a) Sec 4.1 and Fig 4-3] The CC1352 SSI insists on pulsing /CS high between bytes if SPH=0 [Ref TRM (SWCU185D) Sec]

I suspect you'll have to turn the FSS pin into a GPIO and drive /CS low and high yourself.