UART Receiver in Xilinx Spartan 6 FPGA

Thread Starter

Rinnegan

Joined Jan 12, 2019
2
Hello, I am new to FPGAs and trying to make a uart receiver in a Spartan 6 xc6slx9 FPGA. I searced online about Uart receivers but almost all of them use FSMs. I don't yet know about FSMs. I have written a verilog code for the receiver but it doesn't work as intended. Please tell me where I have gone wrong and how to rectify it. Thanks in advance.
Code:
////////////////////////////////////////////////////////////////////////////////////////////////////////////
module UART_RX(clk,d_in,D_Out);
input clk,d_in;//clock & Data input
output [9:0] D_Out;//Data output

reg [9:0] Clock_Divider;
always @(posedge clk)
begin
Clock_Divider <= Clock_Divider+1;
if (Clock_Divider == 54) //for 115200 baud
Clock_Divider <= 0;
end

reg Clk;
always @(Clock_Divider)
begin
if(Clock_Divider == 54)
Clk <= 1'b1;
else
Clk <= 1'b0;
end

reg latch;
always @(d_in or Rst)
begin
if(d_in == 0)
latch <= 1'b1;
if(Rst == 1)
latch <= 1'b0;
end

reg [6:0] Counter;
always @(posedge Clk)
begin
if (latch == 1)
Counter <= Counter+1;
if (Counter == 76)
Counter <= 7'b0000000;
end

reg Rst;
always @(Counter)
begin
if(Counter == 76)
Rst <= 1;
else
Rst <= 0;
end
///////////////////////////////////////////////////
reg SIPO_0;
always @(Counter)
begin
if(Counter==4)
SIPO_0 <= d_in;
end
assign D_Out[0] = SIPO_0;

reg SIPO_1;
always @(Counter)
begin
if(Counter==12)
SIPO_1 <= d_in;
end
assign D_Out[1] = SIPO_1;

reg SIPO_2;
always @(Counter)
begin
if(Counter==20)
SIPO_2 <= d_in;
end
assign D_Out[2] = SIPO_2;

reg SIPO_3;
always @(Counter)
begin
if(Counter==28)
SIPO_3 <= d_in;
end
assign D_Out[3] = SIPO_3;

reg SIPO_4;
always @(Counter)
begin
if(Counter==36)
SIPO_4 <= d_in;
end
assign D_Out[4] = SIPO_4;

reg SIPO_5;
always @(Counter)
begin
if(Counter==44)
SIPO_5 <= d_in;
end
assign D_Out[5] = SIPO_5;

reg SIPO_6;
always @(Counter)
begin
if(Counter==52)
SIPO_6 <= d_in;
end
assign D_Out[6] = SIPO_6;

reg SIPO_7;
always @(Counter)
begin
if(Counter==60)
SIPO_7 <= d_in;
end
assign D_Out[7] = SIPO_7;

reg SIPO_8;
always @(Counter)
begin
if(Counter==68)
SIPO_8 <= d_in;
end
assign D_Out[8] = SIPO_8;

reg SIPO_9;
always @(Counter)
begin
if(Counter==76)
SIPO_9 <= d_in;
end
assign D_Out[9] = SIPO_9;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
Moderators note : used code tags
 
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