The picture i attached, it also looks like two nmos connected in series except the fact that the inputs are kinda weird....
F=(A*~(A))...this function will always output zero ....which makes no sense as a logic gate......
so I believe that this is not an AND Gate?
Well please correct me if i am wrong..
Also, can I interpret that B, ~(B) as Vdd, and ground??
F=(A*~(A))...this function will always output zero ....which makes no sense as a logic gate......
so I believe that this is not an AND Gate?
Well please correct me if i am wrong..
Also, can I interpret that B, ~(B) as Vdd, and ground??
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