deletemeplease

 

A schematic would be helpful buddy.

 

You have to use a p-channel mos for the high side mos because to fully turn on the high side mos you need to apply a voltage 10 volts (as to fully turn it on) above the bus voltage. If it is less than 10 volts above the bus voltage it works in the linear region and gets overheated. Also, this circuit when you turn both mos on will oscillate at a very high frequency (the highest the mos can turn on/off) if your gate voltage on the high side mos is less than Vbus+5 Volts (approximately). This is because when the mos are first switched on the voltage on the source of the high side mos will rise to almost Vbus, this will turn off the high side mos, then the voltage on the source of the high side mos will drop to almost zero, then the upper mos will turn on again and so on.

 

It looks like you're beating up your top FET. The snubber diode D2 should go around only the transformer coil, not that and Q2. The gate is possibly not remaining 10 volts above the source.

Your losses are going to be proportional to the transit times each device spends going from full conduction to full turn off. You can see what each FET is capable of from data sheets, but the drive circuitry - not shown - is what makes the FET's turn off and on.

Question - why are you using two FET's in this circuit? What does Q2 contribute?

 

The snubber diode D2 should go around only the transformer coil, not that and Q2

The schematic is correct for his SMPS topology.

Question - why are you using two FET's in this circuit? What does Q2 contribute?

Allows you to use lower voltage rated FETs and to reduce the amount of leakage inductance energy that has to be dissipated.

If the OP can post his driver circuitry then we might be able to help more.

The OP can try adding a Schottky diode across the upper FET. Its reverse voltage rating should be about 30% higher than the line voltage. You do not need 500V FETs if the input is indeed 240V -- for your topology you do not need 2X the voltage rating.

 

How is the upper MOSFET driven? What is the Vgs for it? Are you sure it is being fully turned on?

 

What I don't understand is how one MOSFET can get substantially hotter than the other MOSFET in a circuit where they are both turned on and off at the same time.

There might be current flowing through the body diode to the input cap when the FETs are turned off.

 

The problem is, I really don't have the equations necessary to calculate what kind of losses I can expect from switching

Most power designers end up measuring this but a good first order equation is:

Psw = ( V^2 * fsw * Id * C_rev_transfer_cap ) / Igate

C_rev_transfer_cap may also be called Crss in the datasheet