Hey,

In my circuit I have two processors connected to one SRAM chip, that is, the address and data lines of both are physically connected to the memory device while the direction of the data is controlled by logic.

One μP writes to the memory and the other reads from it. If the writing μP's address, data, and control lines float so that the other can read what it wrote, will there be any electrical contention between any two devices?

If so, are there any other solutions for this circuit? I could use a data line selector.

From my understanding, "floating", "high impedance", or "tristated" pins are pins which are not driven and have no ground reference.

 

The golden rule is. Several devices my listen to the same buss. But only one can talk at the same time. To get a better understand of your problem, can you post your schematic.
Your defenition of High-Z mode is quite correct as I see it http://en.wikipedia.org/wiki/High_impedance

 

Hey,

In my circuit I have two processors connected to one SRAM chip, that is, the address and data lines of both are physically connected to the memory device while the direction of the data is controlled by logic.

One μP writes to the memory and the other reads from it. If the writing μP's address, data, and control lines float so that the other can read what it wrote, will there be any electrical contention between any two devices?

If so, are there any other solutions for this circuit? I could use a data line selector.

From my understanding, "floating", "high impedance", or "tristated" pins are pins which are not driven and have no ground reference.

as mentioned, you are on the right track. The concern is contention, where the devices require some type of acknowledgement that the buss is free to initiate transfers, or the buss is busy and the device must wait until it is free.

In the older 6502 type micros, one could access alternatively between the phasing, on the 808x/68xxx, wait pins where available. You could employ a cross input to the devices to act as an indicator as to who has buss access.

 

Yep, two processors "A" and "B" can talk to the same memory, but you need some sore of arbitration so they cannot both attempt to talk at the same time. That is at least one line going between processors, "A" tells "B" "get off the memory it is now mine!"

If "B" can instantly release then no worries. You may need to add a delay so A is assured "B" is off, or a second line where "B" tells "A" "I got it."

Even with two lines there exists the chance both will try to grab it at the same microsecond, so when one asserts ownership it needs to check the other is truly off before it begins.

Code very defensively!

 

You also have something named dual port ram Here is a data sheet
http://www.idt.com/products/getDoc.cfm?docID=18654407