Hi guys;

I think my lecturer is being a bit naughty.
Studying for my first tests here... He's given us a piece of VHDL and asked us to do the Truth Table and logic circuit for it.
The answer he's given is basically what looks like a flip flop waveform pattern output.... Hmmm...Well that's not a TT or a logic circuit right?

The logic is -
Y<= (not A0 and not A1 and D0) or
(A0 and not A1 and D1) or
(not A0 and A1 and D2) or
(A0 and A1 and D3);

Now I was having a think about this. Looks easy, but it's tricky... After a number of attempts at wires crossing all over the place and 32 bit truth tables etc...
I think this might be right... Maybe??? What do you think?

 

What do you think?

Your circuit makes no sense. You are shorting some of the inputs and you have gates with a single input from the data lines and wire OR'ing them to an output gate that looks like a single input OR.

I don't think you're going to be able to generate a Kmap by taking short cuts.

 

Well I was thinking about that. In another construction I had 3 channels for the OR gate. But if you think about it - they all then output as Y, right? So is it a shortcut? Or is it perhaps - elegants manifest?

 

Your circuit makes no sense. You are shorting some of the inputs and you have gates with a single input from the data lines and wire OR'ing them to an output gate that looks like a single input OR.

I don't think you're going to be able to generate a Kmap by taking short cuts.

That is the STANDARD shorthand used by PAL devices.
The dots represent intact fuses. The crossed wires without a dot represent "blown" fuses.
The 4 gates on the right are multi-input AND gates with unused inputs tied high.
The single gate in the lower right is a multi-input OR gate with unused inputs tied low.
The result should be an easily decipherable truth table for a multiplexer in SOP form.
Bravo to the TS for figuring out as much as he did.