I teach A level electronics and there is a question I'm stuck on.
Design a transition gate to produce a logic level 0 pulse of duration 15 ns, using NAND gates only. Each NAND gate has a propagation delay of 5 ns.
It's on chapter 3 section 2 page 119 http://resource.download.wjec.co.uk.../16-17_1-9/gce-electronics-book-chapter-3.pdf
The section is about propagation delay and I understand the propagation delay principle.
I can see how you can make a brief logic 0 pulse 15ns delayed passing one input through 3 NANDs configured as NOTs
I cant work out how to make the puls last for 15ns as I think the question asks.
Appreciate any help.
Design a transition gate to produce a logic level 0 pulse of duration 15 ns, using NAND gates only. Each NAND gate has a propagation delay of 5 ns.
It's on chapter 3 section 2 page 119 http://resource.download.wjec.co.uk.../16-17_1-9/gce-electronics-book-chapter-3.pdf
The section is about propagation delay and I understand the propagation delay principle.
I can see how you can make a brief logic 0 pulse 15ns delayed passing one input through 3 NANDs configured as NOTs
I cant work out how to make the puls last for 15ns as I think the question asks.
Appreciate any help.