transistor thermal impedance chart

Papabravo

Joined Feb 24, 2006
13,522
As I see it the vertical axis is thermal impedance (in °K/W), the horizontal axis is pulse width in seconds, and the curve parameter is duty cycle, for a SOT-223 package. What I am missing from this is an actual estimate of the power dissipation. Your impression is correct that, under the assumption of 1W dissipation, there will be a 40 °K rise in temperature from ambient to junction.

Pay attention to Fig. 1, which for the SOT-223 shows a power derating curve which begins at 25 °C and drops pretty quickly for the standard pad footprint. You can improve the situation dramatically by having a 6 cm² pad under the collector. If you can afford the area, I highly recommend doing it or some reasonable compromise between that and the standard footprint.

It looks like the maximum junction temperature is 150 °C
 
Last edited:

Thread Starter

kubeek

Joined Sep 20, 2005
5,718
Yes, but that derating curve is the same thing as the static thermal impedance 125K/W for the 1cm2 SOT223, when you do the junction temperature calculation.
So I think that in case of a pulse load I would do similar calculation with that 40K/W number, so with 1/10 duty cycle each pulse could be up to 3.125W with 25°C ambient and derated in the same way to meet 0W at 150°C ambient.
 

Papabravo

Joined Feb 24, 2006
13,522
Yes, but that derating curve is the same thing as the static thermal impedance 125K/W for the 1cm2 SOT223, when you do the junction temperature calculation.
So I think that in case of a pulse load I would do similar calculation with that 40K/W number, so with 1/10 duty cycle each pulse could be up to 3.125W with 25°C ambient and derated in the same way to meet 0W at 150°C ambient.
I think that would be a valid design. Do you have a way of testing that before committing to copper?
 

Thread Starter

kubeek

Joined Sep 20, 2005
5,718
Not really, copper has to be mada ASAP, or in other words yesterday was almost too late, and validation measuring and argumentation for authorities will come later, just before the second prototype revision will start.
But I am glad that going through the numbers the actual design parameters are not extremely impossible, only just slightly inconvenient ;) The thing here is that the duration of excessive power has to be limited in firmware, and setting the safe limits gets complicated that way.

On another note, do you have any experience taking that datasheet curve and somehow fitting into thermal resistances and capacitances, in such a way that could be easily simulated or calculated to check that the thermal design is ok?
 
Top