# Tone Burst Test Bed

Joined Mar 10, 2018
3,793
I had a requirement to do some filter testing and needed to generate a test

bench with some flexibility.

For this discussion a “component” is an onchip resource.

Below two DDS components generating two tones. Each tones length in # cycles is

controlled by the burst counter. It counts the cycle finished signal coming out of

each wavedac. I choose to have both bursts equal length, could have added another

burst counter so that individual bursts could be controlled. Tones of course different

frequencies.

The system can issue a burst on a key press or put into a mode of generating continuous

bursts. The delay between bursts set by WaveTrainInterval timer/counter.

7 lines of code written, all start instruction for the components. In terms of expediency

while running no user interface is present to control settings, just do that by right clicking

component and entering its settings, then hitting the build/program button. Could have

built user interface but time precluded that and this is a one off.

Code:
int main(void)
{
CyGlobalIntEnable; /* Enable global interrupts. */

/* Place your initialization/startup code here (e.g. MyInst_Start()) */
DDS1_Start( );
DDS2_Start( );
BurstCntr_Start( );
WaveDAC81_Start( );
WaveDAC82_Start( );
Opamp1_Start( );
WaveTrainInterval_Start( );

for(;;)
{
/* Place your application code here. */
}
}
All done on one chip, PSOC 5LP family part. Posted just to show how much can be done

with a programmable routable part with lots of analog and digital resources and not much

coding.

I chose to burst sines but any other arbitrary waveform could have been done. Posted

just to show what todays tools can do and the ease with which ideas can be prototyped

I think I could have fit 4 channels of this on one chip. Not too shabby.

Regards, Dana.

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