I have a few TLE2426CLP TO-92 sometimes called a "rail splitter"
I would like to source 4mA reference and split 5.000Vdc reference, possibly trim dual output reference to ±2.500

The dual polarity supply before used (2) 1% resistors, thermal drift sometimes ±2.547V having 8mV noise

How would you show that the engineered TLE2426 can improve the new supply performance?

The TI TLE2426 datasheet Rail Splitter Precision Virtual Grounds datasheet (Rev. D)

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LTspice updated .subckt for TLE2426 for convenience... I anticipate small VGND stability issues; decoupling and VGND/GND bulk cap.
I can show the circuit, breadboard, multimeter results I hope to make the circuit clear as the forum often gets virtual ground questions.
This is better handled with qualified instruction and a standard circuit that is available is LTspice.

* TLE2426 enhanced behavioral model
* Pins: VIN VOUT GND
.SUBCKT TLE2426 VIN VOUT GND
*.params (tune as needed)
.PARAM Vmin=3.6     ; minimum VIN for regulation (V)
.PARAM Rout=0.8     ; output impedance (ohms)
.PARAM gm=20        ; loop transconductance (S)
.PARAM Imax=35m     ; approx max source/sink (A)
.PARAM Vhead=0.1    ; headroom around target for softer limiting (V)

* Compute regulation target (midpoint)
BVTGT VTGT GND V = { V(VIN,GND)/2 }

* Error between target and actual output
BVER VERR GND V = { V(VTGT,GND) - V(VOUT,GND) }

* Regulation enable based on VIN >= Vmin
* EN is 1 when VIN >= Vmin, else 0 (no regulation; output floats via Rout)
BEN EN GND V = { V(VIN,GND) >= Vmin ? 1 : 0 }

* Ideal drive current before limiting
BIDR IDR GND I = { EN * gm * V(VERR,GND) }

* Soft current limiter: clamp to +/- Imax as error grows
* Linear region within +/-Vhead around target; clamps outside
BILIM ILIM GND I = {
  EN ? limit( gm*V(VERR,GND), -Imax, Imax ) : 0
}

* Drive output with limited current
GOUT VOUT GND VALUE = { I(V(ILIM,GND)) }

* Output resistance (provides load sharing and droop)
Rout VOUT GND {Rout}

* Small numerical stabilizers (optional)
Cstab VOUT GND 1u
Rstab VERR GND 1Meg

.ENDS TLE2426

 

I would like to source 4mA reference and split 5.000Vdc reference, possibly trim dual output reference to ±2.500

How do you mean to trim the output, what is there to trim?

 

sghioto, Thank you for your reply

I want the TLE2426 to have the best advantage in actively balancing the positive and negative.
I may have spoken too soon about needing to make any further adjustment,
If the TLE2426 output is above ±2.500V I might be able to use the trim pin on the ADR435 I forgot to mention.
ADR435B See page 8 ADR430/ADR431/ADR433/ADR434/ADR435 (Rev. N)
Thinking about changes in load is correcting to maintain ±center point.
To make it more useful a buffer with the goal of supplying 25mA, ± 2.500 Vdc low noise.

The TLE2426 datasheet could have shown a precision circuit so I am asking AAC to advise to rectify that and so that
our dual supplies will improve in both understading and accuracy. I think the equivalent circuit is an op amp, precision divider with low TC,
the gain is at least unity and there is improvement to lower noise. Using a rail splitter was recommended earlier. I underestimated it's value.

 

If you are really building something, use the TLE2426. If this is just a SPICE project, use two 2.5V sources to make a 5.0V.

 

Well the TLE2426 can source +/- 20mA with a noise figure of 120uV (reduced to 30uV on SOIC package with 1uF from pin 8 to ground). Output, for 5v in, is 2.5v+/-25mV with worst case regulation is +/- 250uV for 0 - 10mA across the full temperature range. A simple non-inverting good low-noise opamp buffer eg AD797 (0.9nV/√Hz), a precision reference eg LM4040 (0.5%) and external 25k 1% resistor would give 72uV noise with similar regulation to 25mA, but could source 40mA with +/-15mV regulation - but much more expensive.

Go with the TLE2426, you won't easily do better - and for 99% of applications you don't need to.

 

As Irving mentions, the SOIC8 version has a terminal for noise reduction, which in theory, at least from the block diagram, could help you trim the output voltage if so required.

This is similar to the control voltage pin on the 555, which for normal operation a bypass cap is either employed or left open, but it is also used to alter the device timing characteristics.

 

The initial logic for visualizing the Load 5V and 4mA is 625Ω
The split in the current path has a VGND not connected to earth GND this step below is the Ltspice setup.
The dual polarity now has 312.5Ω Load R1 and R2 The 4mA is now 2mA R1 and 2mA R2

VGND is not connected to Earth GND, when TLE2426 is not followed by a buffer any changes in R1 or R2
could cause VGND imbalance to engage the op amp to make adjustment.

If we use the term VGND is not tied to Earth GND. It can help the logic in relating this term to the Math.
A ballon can float away but the ballon does not float downward to the earth (oh yeah) so that there is less confusion by adopting
the simple positive and negative direction that our mechanical math procedure is clearly stated.
It is the op amp that keeps the balloon floating at the same altitude by correcting for load imbalance maintained at 312.5
in line 4 below, the zero node is finite zero. As a result when we click run, the system equations must orbit around that point.
Since the TLE2426 resistors are matched and drift is low the Node zero has finer resolution as an important set midpoint.

Line 1 could be replaced with dual op amp subcircuit. Ron Simpson related this "if you want a real-world circuit."
There are other Caveats also that are significant, the IN is power input but not signal input. The SOIC8 has the trim pin.
I cannot say what is most important. I think the more experienced members are supplying what is missing in that datasheet
and the thread would need to be vetted to get a concise TLE2426 datasheet. Which examples should be included.
Where am I going with this? I am being verbose because students sent here by teachers In order to solve this effectively.
When the forum responds the teachers can adjust for which future changes will absolutely need this, so let's sum this up!

LTspice setup

V1 IN 0 DC 5
X1 IN VGND tle2426
R1 IN VGND 312.5
R2 0 VGND 312.5
.model tle2426 tle2426

 

How to trim the TLE2426CDR ADJ 8-SOIC
TLE2426CDR _Trim.exe example adjusting pin 5 to lower 3mV, but this is not hard to figure out.
You can do this without Ltspice or Trim.exe but the example below can act as a sobriety check or review.

Enter Vcc (in volts): 5.006
Enter target positive rail (in volts): 2.500

--- Results ---
Vcc/2 midpoint: 2.503 V
Target output: 2.500 V
Suggested resistor values:
R1 (to Vcc): 100240 Ω
R2 (to GND): 100000 Ω

By reversing the resistors the trim direction is upward, this forces a shift in the internal divider
however if you raise the positive pole 10mV the negative pole will decrease 10mV.
The trim pin is most awesome when it is needed.
thanks Irving and Schmitt Trigger, ======= appropriate noise comparison post #5
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The role of the bulk capacitor and the bypass capacitor plumbing.
The bulk like 220uF Ecap is a storage reservoir to meet the needs in peak demand.
the 10nF ceramic bypass capacitor delivers quick burst as needed to prevent hiccups.
This is much the same with 555, Bulk also reservoir for current and bypass to filter fast high frequency transients.

 

The TLE2426 is great. . . except that it doesn't do 3.3V supplies. I'm surprised that a 3.3V was never developed, perhaps it would be a TLV2426. Or is everyone happy with an op-amp and two resistors?

 

Ian;
I have heard that same comment a couple of times already.

 

I found this idea on TI’s forum.

With an INA500 or something similar, it will nicely spilt a 3.3V rail.