Timing diagram of a FSM

Hi,

I am not sure whether it is consider inappropriate when I ask two questions consecutively....I just asked one a moment ago, but really these are the type of questions I failed to do every time I encountered them. I think I must misunderstand something...

So here is the question.


Part a) of the question asks me to produce a ASM diagram with RTL operations, and I have no problem doing that. I find it difficult when it comes to question b), which asks me to produce a timing diagram of the FSM with given parameters.



In the end, I have seen the answer and I get everything correct but X and Y.





I do not understand why, in X, xAA lasts for two clock cycles. In its second clock cycle, the system already enters ADD state, so shouldn't Val 2 be loaded into X? The same question appears when it comes to Y. Why is xDD updated at the end of the DONE state?

I once doubt if all of this happened because of the Tcko between state/value transition. Please kindly gimme some guidance on this particular question. Thank you very much.