Hello,

I'm wondering how a timing diagram for a positive triggered master/slave d flip flop looks like. Mainly I am curious about the storage process but I have not found anything in the web. Quite a lot about JK flip flops but not that much about the ms slave ff. Has anyone an example or a web page to look for that?

Thanks a lot!

 

 

Thanks a lot for your help! But I think this one is a negative triggered master/slave d flip flop. On the right you can see it. A positive edge triggered one must have two negations.

Thanks.

 

Just follow the rules described but for the opposite clock edge and construct your own diagram.

 

There are several different master-slave topologies and each has it's own behavior. Just saying positive triggered isn't enough. Is it level-triggered? Edge-triggered? Furthermore, what is it that is happening on the trigger? Is the data captured? Is the output updated? Both?