Time step too small problem in LTSPICE

WBahn

Joined Mar 31, 2012
24,970
I can't open the PDF file from the external site and I'm not going to open archives from unknown sources. You might take a screen shot of the schematic and post it here (after adjusting the size to something reasonable).

Usually the time-step too small error is a result of the failing to converge. This can be caused by a few things. An input that changes too fast is a common culprit. Floating nodes (nodes without a DC path) can also cause problems.
 

ci139

Joined Jul 11, 2016
973
disable too fast voltage and current changes (insert small resistances (mΩ) , avoid small inductors(also Resistors that have inductance at high frequency(kΩ)))

stabilize your grid (bigger or fine tuned capacities to feed lines)

vary simulation time parameters

vari simulation options
 
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ci139

Joined Jul 11, 2016
973
if you use digital inverters then they have specified output voltage and no much limiting output resistance (as if you use a different supply for each)
what you want to do is somewhat complex - uncouple the digital inputs using voltage dependent voltage sources and uncouple the digital outputs using voltage controlled switches (2 one for Vdd one for Vss (or GND if so)) (specifying the apropriate output resistance for - about 1kΩ for CMOS logic)
 

ci139

Joined Jul 11, 2016
973
the digital part does not seem to cause the problems . . . so ignore modifying digital

? the upper LT1762 ? it's IN to GND seems negative -40V ??? near startup (using alternate solver + some minor modifs. near all 3 voltage sources to make it run over 120+ns -- i don't quite grasp what it should do) then gets +100mV (it is possible to load the grid into normal op.-g voltages and then go with warm start ... if you know what they are ...)

? the optos have 1 to 4 N/C:N/C ?? there's no floating node error yet?

i believe it can be simulated with reasonably powerful computer at reasonable time
 
Ltspice : Time step too small Error
I am trying to simulate this Chua's Circuit. The right half of the circuit consisting of U1, U2 and U3 is running fine when simulated separately. But with C1, C2 and GIC inductor, it is giving error.IMG_20191119_161441.jpgIMG_20191119_161532.jpg
 
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