Hi,

what does Vref(threshold voltage) mean for Controller specified in the datasheet? And how does it affect setup and hold time with change in its value?
Suppose i have processor with Vref=3V and SRAM with Vref=1.5V and i have to interface them, how should i analyse the change in parameters due to change in Vref. OR how can i make Vref same for both the components and find out new setup and hold times.......so that i can analyse the interfacing between them.

 

can you show "the datasheet"?

 

Or MCU P/N to look for

 

Vref normally refers to a reference voltage. In MCUs that have ADC capability, Vref (or Aref) would likely be the reference voltage for the analog to digital converter. I've never heard of SRAM having a specification for Vref.

Part numbers would be a real help.

 

Here Vref means Timing reference level (you can refer datasheet of SRAM
CY7C1361C page 24, note no.18)
i want to understand how should we analyze the interface of two components having different timing reference levels...

 

as long as you have the same operating voltage for both devices, they should interface when using the correct commands and protocols.
the issue you may have is that maybe your uP is addressing too fast for the SRAM, in this case you need to slow the uP down.
do you ask because you have a hardware issue or because this is a theoretical problem?

 

What they are talking about in this case is the voltage at which the engineer specifies that the event in question is to be considered to have occurred. This is arbitrary and is usually nothing to worry about as long as the speed of the SRAM is compatible with the MCU.

However, the chip in question is a 3.3V SRAM chip. You need to make sure that the MCU is either operating at 3.3V too, or that the SRAM is tolerant of 5V signals. If not, you will have to do some level shifting. In this case, I do not think the CY7C1361C is a 5V tolerant chip, so you must use it with a 3.3V MCU or employ level shifting.

 

Hi,
can you elaborate it in terms of setup time and hold time? i am not getting it.......

 

Hi,
can you elaborate it in terms of setup time and hold time? i am not getting it.......

Setup time :It is the minimum time before the clock edge the input should be stable.This is due to the input capacitance present at the input.It takes some time to charge to the particular logic level at the input.

Hold time:It is the minimum time the input should be present stable after the clock edge.This is the time taken for the various switching elements to transit from saturation to cut off and vice versa.

So basically set up and hold time is the window during which the input should be stable.Any changes in the input outside the window period may lead to voltage levels which is not recognized by the subsequent stages and the circuit may go to metastable stage.

VREF function varies from device to device.In some uC having in built ADC, it is ADC ref vtg while in some uC's it can be used to re-enumerate uC etc.
Hope that helped!