i need to write an test bench for this waveforms

for now i hav writed this:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY circuitoX IS
PORT(A,B,C: IN BIT; Y:OUT BIT);
END circuitoX;

ARCHITECTURE testbench_arch OF circuitoX IS
SIGNAL A,B,C,Y : BIT;
BEGIN
A<='1'; -- dont now how to define it (looks like an clock)
B<='0','1' AFTER 20 ns,'0' AFTER 60 ns;
C<='0','1' AFTER 40 ns,'0' AFTER 80 ns;
Y<=???? AFTER ?? ns; --i have no idea of what will be the out
END testbench_arch;

can somebody give me tips concerning this code
I am with problems for the A entrance that seems to be one clock and for the exit Y which i have no idea what will be

perhaps it can use this for the A

case A is
when '0' => A <= '1' AFTER 10 ns
when '1' => A <= '0' AFTER 10 ns
end case;

or

A: Process is
Begin
A<=’0’ after 10ns, ‘1’ after 20ns;
Wait for 20ns;
End process A;

Thanks for your precious help

 

i hav found this interesting link to generate vhdl testbenches
take an look at it.
http://www.vhdl-online.de/TB-GEN/ent2tb1.htm