# Synchronous Counter Mod-12 Up/Down Exercise

Discussion in 'Homework Help' started by Alex Lindemann, Jul 16, 2016.

1. ### Alex Lindemann Thread Starter New Member

Jul 16, 2016
4
0
"Design a Synchronous Counter Mod-12 Up/Down, using only Flip-Flop Type D. A binary input $U$ that determines if the counter has to increase ($U = 1$) or decrease ($U = 0$)"

I know the formula for a Flip-Flop Type D is $Q_{t + 1} = D$
So, this is the truth table I did:
$\begin{array}{|c|c|c|c|c|c|c|c|c|c|c|c|c|}
\hline
\large{q_3} & \large{q_2} & \large{q_1} & \large{q_0} \large{q_3'} & \large{q_2'} & \large{q_1'} & \large{q_0'} \large{D_3} & \large{D_2} & \large{D_1} & \large{D_0} & \large{U}\\
\hline\\
\hline\\
0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & -\\
\hline\\
0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & -\\
\hline\\
0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & -\\
\hline\\
0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & -\\
\hline\\
0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & -\\
\hline\\
0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & -\\
\hline\\
0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & 1 & -\\
\hline\\
0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & -\\
\hline\\
1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & -\\
\hline\\
1 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & -\\
\hline\\
1 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & -\\
\hline\\
1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & -\\
\hline\\
1 & 1 & 0 & 0 & - & - & - & - & - & - & - & - & -\\
\hline\\
1 & 1 & 0 & 1 & - & - & - & - & - & - & - & - & -\\
\hline\\
1 & 1 & 1 & 0 & - & - & - & - & - & - & - & - & -\\
\hline\\
1 & 1 & 1 & 1 & - & - & - & - & - & - & - & - & -\\
\hline
\end{array}$

I actually don't know what I should put in the $U$ column, since that one is up to the one using the device, meaning that the one using it says if he wants to count up or count down. Should I put all "don't care" ( "-" ) like I did?
I did the Karnaugh maps already but without counting the $U$ column and the results are the following:
$D_3 = q_3 q_2 q_0 + q_3 q_1 q_0$
$D_2 = \overline{q_3} \overline{q_2} q_1 q_0 + q_2$
$D_1 = \overline{q_1} q_0 + q_1 \overline{q_0}$
$D_1 = \overline{q_0}$
Are these correct?
P. S. It seems that the truth table is not loading correctly. Maybe it's too big? In any case, this is the LaTeX code of it:
\begin{array}{|c|c|c|c|c|c|c|c|c|c|c|c|c|}
\hline
\large{q_3} & \large{q_2} & \large{q_1} & \large{q_0} \large{q_3'} & \large{q_2'} & \large{q_1'} & \large{q_0'} \large{D_3} & \large{D_2} & \large{D_1} & \large{D_0} & \large{U}\\
\hline\\
\hline\\
0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & -\\
\hline\\
0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & -\\
\hline\\
0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & -\\
\hline\\
0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & -\\
\hline\\
0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & -\\
\hline\\
0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & -\\
\hline\\
0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & 1 & -\\
\hline\\
0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & -\\
\hline\\
1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & -\\
\hline\\
1 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & -\\
\hline\\
1 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & -\\
\hline\\
1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & -\\
\hline\\
1 & 1 & 0 & 0 & - & - & - & - & - & - & - & - & -\\
\hline\\
1 & 1 & 0 & 1 & - & - & - & - & - & - & - & - & -\\
\hline\\
1 & 1 & 1 & 0 & - & - & - & - & - & - & - & - & -\\
\hline\\
1 & 1 & 1 & 1 & - & - & - & - & - & - & - & - & -\\
\hline
\end{array}

2. ### dl324 Distinguished Member

Mar 30, 2015
4,244
839
Welcome to AAC!

Can't read the truth table. It's okay to post a picture of a hand drawn table or something entered in a spreadsheet. Once you've done a few tables and generated the Kmaps from them manually, you'll do what I did and make a spreadsheet that populates the Kmaps from the truth table.

If you don't incorporate U in your table and maps, you won't get the correct logic.

3. ### shteii01 AAC Fanatic!

Feb 19, 2010
3,693
555
Yeah. Don't bother with pasting tables.
Take the screen shot, edit it to show what you want, attach it as a jpeg/png/etc.

4. ### Papabravo Expert

Feb 24, 2006
10,689
1,983
Do the states have to belong to the set {0, 1, ...,11} or can they use something like {4, 5, ..., 15}. Both state sequences are modulo 12

5. ### Alex Lindemann Thread Starter New Member

Jul 16, 2016
4
0
I don't know, but the professor always made us do it as a set from 0 to N - 1. (for any kind of module-N)
Thank you for welcoming me!
I uploaded a picture in this post.
How do I incorporate U in the K-maps? Should I do a K-map with 5 entries? I've never done that before. How does it work?

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6. ### Papabravo Expert

Feb 24, 2006
10,689
1,983
If it is not explicitly stated in the requirements then I think you're free to do what makes sense. I would note that such adjustments to a design usually have numerous benefits in practice. In industry, no reasonable manager would put such a restriction on your creativity. Using discrete chips, there can be a considerable saving in board real estate and chip count. Using an FPGA, maybe not so much. Still it is refreshing to take your head out of the .... ah box, so to speak.

7. ### Alex Lindemann Thread Starter New Member

Jul 16, 2016
4
0
So, in your case, from 4 to 15, should I then put the first four rows with "don't care" instead of the last four? It just changes how you write the circuit later but the functionalities are the same, right?

8. ### dl324 Distinguished Member

Mar 30, 2015
4,244
839
It's good manners to welcome people on their first post. We get snippy with members who don't try to solve their problems and post their work so we can give hints. You got off on the right foot.

When is your assignment due?
Here's the table, rotated for easier reading.

Your table needs all 5 variables. You have only entered half of the data. Move U to the leftmost column and add the data for U=0.

5 variables is probably the largest you can do in one table; just remember mirroring. There are You Tube videos from some professors showing how to do 6 variable Kmaps.

9. ### Papabravo Expert

Feb 24, 2006
10,689
1,983
Not quite. They are not exactly don't cares, they are illegal states. I would implement a a fail safe strategy that maps the illegal states belonging to {0,...,3} into a legal state, such as 4. So for all states in {0, ..., 3, 15} the next state would be state 4. If the counter states are {Q3, Q2, Q1, Q0} then the RESET condition for UP would be:

RESET = (Q3 & Q2 & Q1 & Q0) | (!Q3 & !Q2)

In the case of the up down counter you need to implement both RESET to lowest state and RESET to highest state. It should also be evident that there are 16 unique state diagrams diagrams depending on the choice of the starting state, which then defines the ending state. This assumes you want the same set of states for UP and DOWN.

Last edited: Jul 17, 2016
10. ### dl324 Distinguished Member

Mar 30, 2015
4,244
839
For verification, I designed the circuit using don't cares and dealing with illegal states explicitly. As long as the counter is initialized to a valid count, it doesn't matter from a functionality perspective. From a logic standpoint, using don't cares gives simpler logic.

Personally, I would have gone the route suggested by @Papabravo. If I had to actually implement the circuit, I'd be inclined to use don't cares.

11. ### dl324 Distinguished Member

Mar 30, 2015
4,244
839
The first 2 are incorrect, the last 2 are correct.

In your D3 table, you have a group of 4 and 2 groups of 2. That should give you 3 minterms.

In the D2 table, you have a group of 4, a group of 2, and a group of 1. That should give you 3 minterms. To get a minterm with a single variable, you need a group of 8; which you don't have.

12. ### Alex Lindemann Thread Starter New Member

Jul 16, 2016
4
0
Sorry for the late reply! I've been busy recently.
Ugh! I don't know how to do that in the exercise. The prof always told us to put "don't care". :S

You're right, I did it wrong.
It's $D_3 = q_3 \overline{q_1} + q_2 q_1 q_0 + q_3 q_1 \overline{q_0}$
and $D_2 = q_2 \overline{q_1} + \overline{q_3} \overline{q_2} q_1 q_0 + q_2 q_1 \overline{q_0}$
Right?

But, anyway, did you all say that I should add the U into the K-maps? How does it work?

13. ### Papabravo Expert

Feb 24, 2006
10,689
1,983
You use a 4 input AND gate to decode {1,1,1,1}, You use a 2 input NOR gate to decode {0,0,x,x}, and finally you combine those two results with a 2 input OR gate. Stop being a twit and hiding behind your interpretation of what you think the professor said. If the two most significant bits of the state {q3,q2} are both 0, that represents an illegal state. The don't cares are the two least significant bits {q1, q0}. Bits {q3, q2} are most definitely NOT don't cares. Bits {q1, q0} are most definitely don't cares. Got it?

14. ### dl324 Distinguished Member

Mar 30, 2015
4,244
839
There's not much point in checking your work when it's not for the right problem.
You just build a table with 5 variables, one of which is the up/down control signal. With 5 variables, your table will have twice as many rows.

The way I was taught to do Kmaps was to put the most significant bits on the left and the least significant on the top; that allows you can read the bit patterns in a more natural left to right order.

15. ### dl324 Distinguished Member

Mar 30, 2015
4,244
839
That doesn't apply to synchronous counter design. In synchronous counter design, illegal states aren't generated; as long as the flip flops are initialized to a valid state.

16. ### WBahn Moderator

Mar 31, 2012
19,125
5,171
Relying on any state machine to simply not generate illegal states is NOT good design practice. What if one of the bits gets flipped due to a power supply glitch or a cosmic ray hitting the circuitry? State upsets happen. Your system should, by design, behave reasonably given any state condition. Sometimes this means that you want to ensure that the state walks itself out of the bad state and back into the normal cycle of things. Sometimes this means that you want to ensure that the state does NOT walk itself out of the bad state but, instead, traps itself in a bad-state condition.

17. ### Papabravo Expert

Feb 24, 2006
10,689
1,983
It most certainly does apply to synchronous counter design. It is just good practice and costs very little in the modern FPGA.

18. ### Papabravo Expert

Feb 24, 2006
10,689
1,983
In software you hope that bugs have enough observable features so you can see them quickly and fix them. Making the error obvious in hardware seems reasonable. I actually hadn't thought about trapping the counter in an illegal state.

19. ### WBahn Moderator

Mar 31, 2012
19,125
5,171
It all depends on the application. In many of the chips we designed we used a Gray code counter that was not initialized and could actually start up running backwards (in fact, it did that about half the time). But the counter design meant that if it did start up running backwards that, when it overflowed, it would start running forward from that point on. That was good enough because it meant that the first image out of the imager was trash -- but then it was trash for a host of other reasons as well, so who cared? The bad thing about this circuit is that it made simulating the circuitry faithfully impossible since simulators don't like circuits whose behavior relies on uninitialized charge storage nodes.

On other systems if the state machine ended up in a bad state, that could mean that a whole host of things might have gone wrong and, due to the potential consequences for the imagers if the DC balance was not rigorously maintained, it was deemed best to let the controller hang. Since the controller loop sent a square wave to a charge pump that was used to prevent a set of crowbar switches (transistors) across the power supplies from slamming shut, if anything happened to the controller (including the cable connecting it to the board coming disconnected), the crowbars would clamp across the supplies in a matter of a few milliseconds which would save the (very expensive) imager. The supplies and switches, of course, were designed to handle this condition.