Our professor wants us to make a program in MLab to show an output of the basic logic gates using pic18f where the inputs(switches) will be assign assign in RA1 and RA2

RB0 = RA1 + RA2
RB3 = RA1 * RA2
RB4 =RA1 xor RA2
RB7 =RA1 xnor RA2
also he don't want us to use bit oriented operation so we must use byte oriented operation only and no using of C programming

 

Wow ! how to you use a PIC without programming.

 

Like this

#include "P18F4550.inc"
  
config  FOSC = HS        
config  CPUDIV = OSC1_PLL2 
config  PLLDIV = 1  
config  PWRT = OFF  
config  BOR = OFF  
config  WDT = OFF  
config  MCLRE = ON  
config  STVREN = ON  
config  LVP = OFF 
config  ICPRT = OFF  
config  XINST = OFF  
config  DEBUG = OFF  
config  FCMEN = OFF
config  IESO = OFF 
config  LPT1OSC = OFF 
config  CCP2MX = ON  
config  PBADEN = OFF
config  USBDIV = 2
config  VREGEN = OFF
 
R1    equ 0x000  
R2    equ 0x001
  
 
org 0x0000
  
BRA START

org 0x0008
RETFIE FAST
  
org 0x0018
RETFIE
  
START
; Initialization
; Disable analog comparators multiplexed on RA and RB
MOVLW 0x0F
MOVWF ADCON1, ACCESS 
MOVLW 0x07 
MOVWF CMCON, ACCESS

; Initialize RA[1-2] as input: the rest as output  
; Initialize RB[0-7] as output
; Initialize RD[0-7] as output 
MOVLW 0x06 
MOVWF TRISA, ACCESS 
CLRF TRISB, ACCESS
CLRF TRISD, ACCESS
  

LOOP
 
;SEQUENCE 0
MOVF PORTA,W,ACCESS;0000 0000/0000 0010
MOVWF LATB,ACCESS

; Sequence 1
; Read current logic levels of pins of RA then store to memory location R1 
MOVF PORTA, W, ACCESS
    ;0000 0010
MOVWF R1, ACCESS
  
;0000 0010
; Complement the current value of R1 
COMF R1, F, ACCESS
    ;1111 1101
  
; Shift to the right 
RRNCF R1, F, ACCESS
   ;1111 1110
  
; Cancel out all other bits except bit 0
MOVLW 0x01
             ;0000 0001
ANDWF R1, F, ACCESS
   ;0000 0000

; Send the current value of R1 to LATA
MOVF R1, W, ACCESS
    ;0000 0000
MOVWF LATA, ACCESS
  
MOVF PORTA,W,ACCESS
MOVWF R1,ACCESS ; 0000 0000 / 0000 0010
COMF R1,F,ACCESS ;1111 1111 / 1111 1101
RLNCF R1,F,ACCESS;
RLNCF R1,F,ACCESS;
RLNCF R1,F,ACCESS;
RLNCF R1,F,ACCESS;1111 1111 / 1101 1111
MOVLW 0X20;        0010 0000
ANDWF R1,F,ACCESS;0010 0000 / 0000 0000
MOVF R1,W,ACCESS; 0100 0000 / 0000 0000
MOVWF LATB,ACCESS;0100 0000 / 0000 0000

; Sequence 2
; Read current logic levels of pins of RA then store to memory location R1
  
MOVF PORTA, W, ACCESS
MOVWF R1, ACCESS
  
;0000 0000    / 0000 0100

; Complement the current value of R1
COMF R1, F, ACCESS
  ;1111 1111  
/1111 1011  
; Shift to the right five times (5x)
  
RLNCF R1, F, ACCESS
   ;1111 1111 /1111 0111
RLNCF R1, F, ACCESS
   ;1111 1111 /1110 1111
RLNCF R1, F, ACCESS
   ;1111 1111 /1101 1111
RLNCF R1, F, ACCESS
   ;1111 1111 /1011 1111
RLNCF R1, F, ACCESS
   ;1111 1111
/0111 1111  
; Cancel out all other bits except bit 7 
MOVLW 0x80
  
ANDWF R1, F, ACCESS
  
;1000 0000    /0000 0000

; Send the current value of R1 to LATD 
MOVF R1, W, ACCESS
  
MOVWF LATD, ACCESS

MOVF PORTA,W,ACCESS
MOVWF R1,ACCESS ;0000 0100 / 0000 0000
COMF R1,F,ACCESS;1111 1011 / 1111 1111
RRNCF R1,F,ACCESS;
RRNCF R1,F,ACCESS;
RRNCF R1,F,ACCESS;
RRNCF R1,F,ACCESS;1011 1111 / 1111 1111
MOVLW 0X40;0100 0000
ANDWF R1,F,ACCESS;0000 0000 / 0100 0000
MOVF R1,W,ACCESS
MOVWF LATB,ACCESS;0000 0000 /0100 0000

; Repeat the sequence  
BRA LOOP
end

Mod edit: please use code tags for posting code

 

no using of C programming

Code it in C, then submit the compiler generated disassembly file.

Done.

 

Probably he meant something of that sort

  rrncf PORTA,w ; load data bits x-x-x-x-x-x-A2-A1
  andlw 0x03   ; remove unneeded bits 0-0-0-0-0-0-A2-A1
  addlw 0x7d   ; calculate the required entities and simultaneously separate (A1*A2) from (A1+A2)
               ; result: (A1*A2)-x-x-x-x-x-(A1+A2)-0
  rrncf WREG,w ; shift it to the very right x-(A1*A2)-x-x-x-x-x-(A1+A2)
  andlw 0x41   ; clean-up 0-(A1*A2)-0-0-0-0-0-(A1+A2)
  addlw 0x4f   ; shift (A1*A2) and (A1+A2) into the places and simultaneously
               ; calculate nxor - (A1*A2)-x-0-(A1+A2)-x-x-x-(A1 nxor A2)
  andlw 0x91   ; clean-up (A1*A2)-0-0-(A1+A2)-0-0-0-(A1 nxor A2)
  addlw 0x07   ; shift (A1 nxor A2) into the place and simultaneously calculate
               ; xor - (A1*A2)-0-0-(A1+A2)-(A1 nxor A2)-x-x-(A1 xor A2)
  swapf WREG,w ; now everything is as requested (A1 nxor A2)-x-x-(A1 xor A2)-(A1*A2)-0-0-(A1+A2)
  xorwf LATB,w ; to avoid disturbing unused bits in port B do a XOR swap
  andlw 0x99
  xorwf LATB,f ; done

edit: fixed a bug. First line - needs to read PORTA, not LATA.

 

NorthGuy

I can't imagine the output since I don't know the value of LATB before the operation xorwf LATB,w. Can you please show the output if RA1 =1 and RA2 =1

rrncf LATA,w ; load data bits x-x-x-x-x-x-A2-A1                         w =    0000 0011
  andlw 0x03   ; remove unneeded bits 0-0-0-0-0-0-A2-A1                        w =    0000 0011
  addlw 0x7d   ; calculate the required entities and simultaneously separate (A1*A2) from (A1+A2)w =    0111 1101 ->0000 0001
               ; result: (A1*A2)-x-x-x-x-x-(A1+A2)-0
  rrncf WREG,w ; shift it to the very right x-(A1*A2)-x-x-x-x-x-(A1+A2)                w =    1000 0000
  andlw 0x41   ; clean-up 0-(A1*A2)-0-0-0-0-0-(A1+A2)                        w =    1000 0000 & 0100 0001 = 0000 0000
  addlw 0x4f   ; shift (A1*A2) and (A1+A2) into the places and simultaneously            w =    0000 0000 & 0100 1111 = 0000 0000
               ; calculate nxor - (A1*A2)-x-0-(A1+A2)-x-x-x-(A1 nxor A2)            w =  
  andlw 0x91   ; clean-up (A1*A2)-0-0-(A1+A2)-0-0-0-(A1 nxor A2)                w =     0000 0000 & 1001 0001 = 0000 0000
  addlw 0x07   ; shift (A1 nxor A2) into the place and simultaneously calculate            w =    0000 0000 & 0000 0111 = 0000 0000
               ; xor - (A1*A2)-0-0-(A1+A2)-(A1 nxor A2)-x-x-(A1 xor A2)
  swapf WREG,w ; now everything is as requested (A1 nxor A2)-x-x-(A1 xor A2)-(A1*A2)-0-0-(A1+A2) w =     0000 0000
  xorwf LATB,w ; to avoid disturbing unused bits in port B do a XOR swap            w =  
  andlw 0x99
  xorwf LATB,f ; done

 

Code it in C, then submit the compiler generated disassembly file.

Done.

That is terrible advice.

 

NorthGuy
I can't imagine the output since I don't know the value of LATB before the operation xorwf LATB,w. Can you please show the output if RA1 =1 and RA2 =1

You made a number of mistakes following the results of the operation. Here how it goes:

  rrncf PORTA,w;  w =    xxxx xx11
  andlw 0x03   ;  w =    0000 0011
  addlw 0x7d   ;  w =    1000 0000
  rrncf WREG,w ;  w =    0100 0000
  andlw 0x41   ;  w =    0100 0000
  addlw 0x4f   ;  w =    1000 1111
  andlw 0x91   ;  w =    1000 0001
  addlw 0x07   ;  w =    1000 1000
  swapf WREG,w ;  w =    1000 1000

At this point the result is in WREG. You may clean it and write to LATB:

  andlw 0x99 ;  w =   1000 1000
  movwf LATB ; latb = 1000 1000

However, this would clear RB1,RB2,RB5 and RB6. To preserve the values which are there, you do the XOR swap (google it) instead. Say, if LATB was all ones (1111 1111)

  xorwf LATB,w ;  w =   0111 0111
  andlw 0x99   ; w =    0001 0001
  xorwf LATB,f ; latb = 1110 1110

Both version of the ending do the same thing with RB0,RB3,RB4, and RB7 - these get moved from W to LATB. But the first code sets the rest of the bits to 0, while the second one preserves whatever was in these bits before.

 

Much better than looking at the disassembly is simulating every operation separately with MPSIM and then look at the outcome in the watch window.

If you are organized, you could do it in minutes and learn a lot. Otherwise, your classmate from the North is going to take all credits.

 

Thank you very much for correction and clarification
but if the value I use for RA1 =1 and RA2 =1
Doesn't the value when it was send to LATB become this
RB0 =(1)
RB1 =0
RB2 =0
RB3 =(1)
RB4 =(0)
RB5 =0
RB6 =0
RB7 =(1)

 

but if the value I use for RA1 =1 and RA2 =1
Doesn't the value when it was send to LATB become this

No, It becomes 0x88 (10001000). See my previous post for step-by-step values.

Why do you think it has 1 in RB0?

 

No, It becomes 0x88 (10001000). See my previous post for step-by-step values.

Why do you think it has 1 in RB0?

Because in Basic Logic OR
In Truth Table
RA1 RA2 RB0
0 0 0
0 1 1
1 0 1
1 1 1

 

Because in Basic Logic OR
In Truth Table

The assignment says "+" not "or". May be the same if you're taking formal logic classes, but totally different things if you do programming. To see the difference, try these in C:

RB0 = RA1 + RA2;
RB0 = RA1 | RA2;
RB0 = RA1 || RA2;

But, you now know how to do such things, so if "or" is what you want you can modify it to do "or".

 

Here is a C-translated XOR() and AND() operations:

35:                       //xor gate
36:                       if (XOR(XORIN1, XORIN2)) IO_SET(XOROUT_PORT, XOROUT);
   7E5    3000     MOVLW 0
   7E6    1283     BCF 0x3, 0x5
   7E7    1886     BTFSC 0x6, 0x1
   7E8    3001     MOVLW 0x1
   7E9    00F0     MOVWF 0x70
   7EA    3000     MOVLW 0
   7EB    01F1     CLRF 0x71
   7EC    1806     BTFSC 0x6, 0
   7ED    3001     MOVLW 0x1
   7EE    00F2     MOVWF 0x72
   7EF    01F3     CLRF 0x73
   7F0    0670     XORWF 0x70, W
   7F1    00F4     MOVWF 0x74
   7F2    0871     MOVF 0x71, W
   7F3    0673     XORWF 0x73, W
   7F4    00F5     MOVWF 0x75
   7F5    0474     IORWF 0x74, W
   7F6    1903     BTFSC 0x3, 0x2
   7F7    2FFA     GOTO 0x7fa
   7F8    1506     BSF 0x6, 0x2
   7F9    2FFB     GOTO 0x7fb
37:                       else IO_CLR(XOROUT_PORT, XOROUT);
   7FA    1106     BCF 0x6, 0x2
38:                      
39:                       //and gate
40:                       if (AND(ANDIN1, ANDIN2)) IO_SET(ANDOUT_PORT, ANDOUT);
   7FB    1986     BTFSC 0x6, 0x3
   7FC    1E06     BTFSS 0x6, 0x4
   7FD    2FE4     GOTO 0x7e4
   7FE    1686     BSF 0x6, 0x5
   7FF    2FE5     GOTO 0x7e5
41:                       else IO_CLR(ANDOUT_PORT, ANDOUT);

Obviously, for a specific set of input / output configuration.

All done in a few seconds.

 

All done in a few seconds.

First, it used bit operations which are forbidden by the assignment, so the best it can get is probably C-.

Then, if a machine does your assignments for you, don't you think that the machine should get the degree, not you

 

here is the complete implementation of all the four gates, on the same pins the assignment asked for:

54:                       //or gate
55:                       if (OR(ORIN1, ORIN2)) IO_SET(OROUT_PORT, OROUT);
   7D0    1885     BTFSC 0x5, 0x1
   7D1    2FD4     GOTO 0x7d4
   7D2    1D05     BTFSS 0x5, 0x2
   7D3    2FD6     GOTO 0x7d6
   7D4    1406     BSF 0x6, 0
   7D5    2FD7     GOTO 0x7d7
56:                       else IO_CLR(OROUT_PORT, OROUT);
   7D6    1006     BCF 0x6, 0
57:               
58:                       //and gate
59:                       if (AND(ANDIN1, ANDIN2)) IO_SET(ANDOUT_PORT, ANDOUT);
   7D7    1885     BTFSC 0x5, 0x1
   7D8    1D05     BTFSS 0x5, 0x2
   7D9    2FDC     GOTO 0x7dc
   7DA    1586     BSF 0x6, 0x3
   7DB    2FDD     GOTO 0x7dd
60:                       else IO_CLR(ANDOUT_PORT, ANDOUT);
   7DC    1186     BCF 0x6, 0x3
61:               
62:                       //xor gate
63:                       if (XOR(XORIN1, XORIN2)) IO_SET(XOROUT_PORT, XOROUT);
   7DD    1D05     BTFSS 0x5, 0x2
   7DE    2FE1     GOTO 0x7e1
   7DF    3001     MOVLW 0x1
   7E0    2FE2     GOTO 0x7e2
   7E1    3000     MOVLW 0
   7E2    00F0     MOVWF 0x70
   7E3    1C85     BTFSS 0x5, 0x1
   7E4    2FE7     GOTO 0x7e7
   7E5    3001     MOVLW 0x1
   7E6    2FE8     GOTO 0x7e8
   7E7    3000     MOVLW 0
   7E8    0670     XORWF 0x70, W
   7E9    1903     BTFSC 0x3, 0x2
   7EA    2FED     GOTO 0x7ed
   7EB    1606     BSF 0x6, 0x4
   7EC    2FEE     GOTO 0x7ee
64:                       else IO_CLR(XOROUT_PORT, XOROUT);
   7ED    1206     BCF 0x6, 0x4
65:               
66:                       //xNor gate
67:                       if (XNOR(XNORIN1, XNORIN2)) IO_SET(XNOROUT_PORT, XNOROUT);
   7EE    1D05     BTFSS 0x5, 0x2
   7EF    2FF2     GOTO 0x7f2
   7F0    3001     MOVLW 0x1
   7F1    2FF3     GOTO 0x7f3
   7F2    3000     MOVLW 0
   7F3    00F0     MOVWF 0x70
   7F4    1C85     BTFSS 0x5, 0x1
   7F5    2FF8     GOTO 0x7f8
   7F6    3001     MOVLW 0x1
   7F7    2FF9     GOTO 0x7f9
   7F8    3000     MOVLW 0
   7F9    0670     XORWF 0x70, W
   7FA    1D03     BTFSS 0x3, 0x2
   7FB    2FFE     GOTO 0x7fe
   7FC    1786     BSF 0x6, 0x7
   7FD    2FD0     GOTO 0x7d0
68:                       else IO_CLR(XNOROUT_PORT, XNOROUT);
   7FE    1386     BCF 0x6, 0x7
   7FF    2FD0     GOTO 0x7d0

All comes to about 50 bytes.

the chip i implemented this on is a 16F690 so you can disassemble the addresses into macros in order to make it more human-readable. The code actually runs correctly as is.

 

The code I posted earlier provides the most flexibility: each logic function can have its own and different inputs -> in this case, they are configured to the same.

Its downside is that it doesn't maintain atomiocity.

The following implementation maintains atomicity: all logic functions are tested on the same states of the pins so their output is logically consistent at all times.

                      lvar = IO_GET(LIN_PORT, LIN1 | LIN2);    //read the logic input
   7CD    1283     BCF 0x3, 0x5
   7CE    0805     MOVF 0x5, W
   7CF    00F0     MOVWF 0x70
   7D0    3006     MOVLW 0x6
   7D1    05F0     ANDWF 0x70, F
49:                      
50:                       //or gate
51:                       if (OR(LIN1, LIN2)) IO_SET(OROUT_PORT, OROUT);
   7D2    18F0     BTFSC 0x70, 0x1
   7D3    2FD6     GOTO 0x7d6
   7D4    1D70     BTFSS 0x70, 0x2
   7D5    2FD8     GOTO 0x7d8
   7D6    1407     BSF 0x7, 0
   7D7    2FD9     GOTO 0x7d9
52:                       else IO_CLR(OROUT_PORT, OROUT);
   7D8    1007     BCF 0x7, 0
53:                
54:                       //and gate
55:                       if (AND(LIN1, LIN2)) IO_SET(ANDOUT_PORT, ANDOUT);
   7D9    18F0     BTFSC 0x70, 0x1
   7DA    1D70     BTFSS 0x70, 0x2
   7DB    2FDE     GOTO 0x7de
   7DC    1587     BSF 0x7, 0x3
   7DD    2FDF     GOTO 0x7df
56:                       else IO_CLR(ANDOUT_PORT, ANDOUT);
   7DE    1187     BCF 0x7, 0x3
57:                
58:                       //xor gate
59:                       if (XOR(LIN1, LIN2)) IO_SET(XOROUT_PORT, XOROUT);
   7DF    1D70     BTFSS 0x70, 0x2
   7E0    2FE3     GOTO 0x7e3
   7E1    3001     MOVLW 0x1
   7E2    2FE4     GOTO 0x7e4
   7E3    3000     MOVLW 0
   7E4    00F1     MOVWF 0x71
   7E5    1CF0     BTFSS 0x70, 0x1
   7E6    2FE9     GOTO 0x7e9
   7E7    3001     MOVLW 0x1
   7E8    2FEA     GOTO 0x7ea
   7E9    3000     MOVLW 0
   7EA    0671     XORWF 0x71, W
   7EB    1903     BTFSC 0x3, 0x2
   7EC    2FEF     GOTO 0x7ef
   7ED    1607     BSF 0x7, 0x4
   7EE    2FF0     GOTO 0x7f0
60:                       else IO_CLR(XOROUT_PORT, XOROUT);
   7EF    1207     BCF 0x7, 0x4
61:                
62:                       //xNor gate
63:                       if (XNOR(LIN1, LIN2)) IO_SET(XNOROUT_PORT, XNOROUT);
   7F0    1D70     BTFSS 0x70, 0x2
   7F1    2FF4     GOTO 0x7f4
   7F2    3001     MOVLW 0x1
   7F3    2FF5     GOTO 0x7f5
   7F4    3000     MOVLW 0
   7F5    00F1     MOVWF 0x71
   7F6    1CF0     BTFSS 0x70, 0x1
   7F7    2FFA     GOTO 0x7fa
   7F8    3001     MOVLW 0x1
   7F9    2FFB     GOTO 0x7fb
   7FA    3000     MOVLW 0
   7FB    0671     XORWF 0x71, W
   7FC    1D03     BTFSS 0x3, 0x2
   7FD    2FCC     GOTO 0x7cc
   7FE    1787     BSF 0x7, 0x7
   7FF    2FCD     GOTO 0x7cd
64:                       else IO_CLR(XNOROUT_PORT, XNOROUT);
65:

The output port is PORTC. Pin assignment is the same.

 

Is it just me, or you're building your own assembler-like commands on top of the C?

 

Does it work? Check,

Using the code posted earlier.

 

I forgot to post this but this is the output my professor made

   #include "P18F4550.inc"
   
    config  FOSC = HS       
    config  CPUDIV = OSC1_PLL2
    config  PLLDIV = 1 
    config  PWRT = OFF
    config  BOR = OFF
    config  WDT = OFF
    config  MCLRE = ON
    config  STVREN = ON
    config  LVP = OFF
    config  ICPRT = OFF
    config  XINST = OFF
    config  DEBUG = OFF
    config  FCMEN = OFF
    config  IESO = OFF
    config  LPT1OSC = OFF
    config  CCP2MX = ON
    config  PBADEN = OFF
    config  USBDIV = 2
    config  VREGEN = OFF
   
    INPUT   equ 0x000    ; BANK 0
    OUTPUT  equ 0x100    ; BANK 1
    TEMP    equ 0X001    ; BANK 0
   
    org 0x0000
    BRA START
   
    org 0x0008
    RETFIE FAST
   
    org 0x0018
    RETFIE
   
START
    ; Disable Analog Comparators multiplexed with RA & RB
    MOVLW 0x0F
    MOVWF ADCON1, ACCESS
    MOVLW 0x07
    MOVWF CMCON, ACCESS
   
    ; Set the direction of RA[1-2] to INPUT; Rest is OUTPUT
    MOVLW 0x06
    MOVWF TRISA, ACCESS
   
    ; Set the direction of RB[0-7] to OUTPUT
    CLRF TRISB, ACCESS
LOOP
    ; Init OUTPUT = 0x00
    MOVLB 0x1
    CLRF OUTPUT, BANKED
   
    ; RB[0] = RA[1] OR RA[2]
    ; RB[1] = RA[1]
    ; RB[2] = RA[2]
    ; RB[3] = RA[1] AND RA[2]
    ; RB[4] = RA[1] XOR RA[2]
    ; RB[5] = NOT RA[1]
    ; RB[6] = NOT RA[2]
    ; RB[7] = RA[1] XNOR RA[2]
    ; MOVWF LATB, ACCESS ONCE
   
    ; Read the cuurent logic of the switches
    MOVF PORTA, W, ACCESS
    MOVWF INPUT, ACCESS
   
    ; RB[1|2] = RA[1|2]
    ANDLW 0x06
    MOVLB 0x1
    MOVWF OUTPUT, BANKED
   
    ; RB[5|6] = NOT RA[1|2]
    MOVF INPUT, W, ACCESS
    MOVWF TEMP, ACCESS
    COMF TEMP, F, ACCESS
    SWAPF TEMP, W, ACCESS
    ANDLW 0x60
    MOVLB 0x1
    IORWF OUTPUT, F, BANKED
   
    ; RB[0] = RA[1] OR RA[2]
    MOVF INPUT, W, ACCESS   ; R1
    MOVWF TEMP, ACCESS       ; R2
    RRNCF TEMP, F, ACCESS   ; BIT 1
    IORWF TEMP, F, ACCESS
    RRNCF TEMP, W, ACCESS
    ANDLW 0x01
    MOVLB 0x1
    IORWF OUTPUT, F, BANKED
   
    ; RB[3] = RA[1] AND RA[2]
    MOVF INPUT, W, ACCESS   ; R1
    MOVWF TEMP, ACCESS       ; R2
    RLNCF TEMP, F, ACCESS   ; BIT 2
    ANDWF TEMP, F, ACCESS
    RLNCF TEMP, W, ACCESS
    ANDLW 0x08
    MOVLB 0x1
    IORWF OUTPUT, F, BANKED
   
    ; RB[4] = RA[1] XOR RA[2]
    MOVF INPUT, W, ACCESS   ; R1
    MOVWF TEMP, ACCESS       ; R2
    RRNCF TEMP, F, ACCESS   ; BIT 1
    XORWF TEMP, F, ACCESS  
    RRNCF TEMP, F, ACCESS
    SWAPF TEMP, W, ACCESS
    ANDLW 0x10
    MOVLB 0x1
    IORWF OUTPUT, F, BANKED
   
    ; RB[7] = RA[1] XNOR RA[2]
    MOVF INPUT, W, ACCESS   ; R1
    MOVWF TEMP, ACCESS       ; R2
    RLNCF TEMP, F, ACCESS   ; BIT 2
    XORWF TEMP, F, ACCESS
    COMF TEMP, F, ACCESS    ; XNOR
    RLNCF TEMP, F, ACCESS
    SWAPF TEMP, W, ACCESS
    ANDLW 0x80
    MOVLB 0x1
    IORWF OUTPUT, W, BANKED
   
    MOVWF LATB, ACCESS
   
    BRA LOOP
   
    end