Hello

I have a few questions about the clock system in the stm32F4 MCU .
I understand that there is a system clock with a max speed of 168 , then there are the ABP1 ,ABP2 busses with
maximum speeds of 48Mhz and 84Mhz respectively.
I've used the stm32 excel clock tool and successfully clocked the MCU at 168Mhz Using the External Xtal as the source.

My question: What speed are the ABP1/2 and AHB busses running at? Can I prescale them from the system clock?
Question 2: Why are there more than one AHB busses? Do they each have their own prescaler from the system clock ?

Thanks in advance

 

Ok so I've found my answer in the system file generated by the STM32 clock tool
Sorry for the "blank" post , I needed an answer fast.

*=============================================================================
  *=============================================================================
  *        Supported STM32F40xx/41xx/427x/437x devices
  *-----------------------------------------------------------------------------
  *        System Clock source                    | PLL (HSE)
  *-----------------------------------------------------------------------------
  *        SYSCLK(Hz)                             | 168000000
  *-----------------------------------------------------------------------------
  *        HCLK(Hz)                               | 168000000
  *-----------------------------------------------------------------------------
  *        AHB Prescaler                          | 1
  *-----------------------------------------------------------------------------
  *        APB1 Prescaler                         | 4
  *-----------------------------------------------------------------------------
  *        APB2 Prescaler                         | 2
  *-----------------------------------------------------------------------------
  *        HSE Frequency(Hz)                      | 8000000
  *-----------------------------------------------------------------------------
  *        PLL_M                                  | 8
  *-----------------------------------------------------------------------------
  *        PLL_N                                  | 336
  *-----------------------------------------------------------------------------
  *        PLL_P                                  | 2
  *-----------------------------------------------------------------------------
  *        PLL_Q                                  | 7
  *-----------------------------------------------------------------------------
  *        PLLI2S_N                               | NA
  *-----------------------------------------------------------------------------
  *        PLLI2S_R                               | NA
  *-----------------------------------------------------------------------------
  *        I2S input clock                        | NA
  *-----------------------------------------------------------------------------
  *        VDD(V)                                 | 3.3
  *-----------------------------------------------------------------------------
  *        Main regulator output voltage          | Scale1 mode
  *-----------------------------------------------------------------------------
  *        Flash Latency(WS)                      | 5
  *-----------------------------------------------------------------------------
  *        Prefetch Buffer                        | OFF
  *-----------------------------------------------------------------------------
  *        Instruction cache                      | ON
  *-----------------------------------------------------------------------------
  *        Data cache                             | ON
  *-----------------------------------------------------------------------------
  *        Require 48MHz for USB OTG FS,          | Disabled
  *        SDIO and RNG clock                     |
  *-----------------------------------------------------------------------------
  *=============================================================================
  ******************************************************************************

 

But perhaps someone could advise as to what the following attributes are and how they can be used/useful :

Flash latency(WS)
Prefetch buffer
Data cache

 

The CPU running at top speed (168MHz) runs faster than the rate at which instructions and data can be fetched from flash memory.
Hence wait states (5) are required between when instruction/data are requested and when they become available.

To overcome this delay, instructions and data are prefetched and stored in the instruction cache and data cache. On normal pipeline execution there is no slowdown until you hit a branch instruction in which case the cache must be refreshed and it cost you a 5 WS penalty.

 

Thanks for the reply. Could you give an example of such a branch instruction which would cost 5 WS?
Am I correct to assume that If I set the system clk to say 16Mhz then I should always set the WS to 1 ?

 

I assume that this is a hypothetical question, i.e. you are not really planning on using an external 16MHz clock.

Typically, one would simply follow the application notes where an 8MHz crystal is employed. The internal configuration will set the PLL so that the correct SYSCLK of 168MHz is generated. Note that you will need 48MHz if you plan on using the on-chip USB functions.

Hypothetically, if you want to decrease SYSCLK to 16MHz, you will need zero WS, i.e. no waiting.

As for a hit/miss in the instruction/data pipeline, if the required data or the next instruction to be executed (i.e. destination of a branch instruction) is not already in the cache, then a miss occurs. The cache has to be refreshed and hence the processor has to wait for the preprogrammed number of wait states before continuing.

 

Thanks for the reply. Yes , it was a hypothetical question.
I'm going to be clocking the stm32 at 84Mhz or 168Mhz for my quadcopter project. The discovery has an 8Mhz external XTAL and I'm going to keep it that way when I make my own board.