Speed of AT89C51 Microcontroller

mvas

Joined Jun 19, 2017
538
I believe, the maximum count rate is 1/24th of the OSC Clock Frequency
and the State of the Input Pin should be held steady for 12 clock cycles ( 1 machine cycle ),
to guarantee that current State is sampled.

Specifically ...
a) The Counter Input Pin is sampled during the S5-P2 execution state.
b) The Count register is updated on the following S3-P1 execution state..
 
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