Hello everyone,

I am studying in class E amplifier that seems very strange. I have always seen a square signal to drive the gate, my amp has a sinusoidal signal instead.

In addition, current and output voltage are not offset in time, but there is simply a very high voltage and current very low as shown:

(The red signal is the voltage on the gate, while the blue signal is the current on it).

What kind of class E amplifier can be? This is a class E?

 

Without a schematic we can't even guess.

 

The waveform certainly looks characteristic of a class E waveform - a bit unoptimised though, as at turn-on the waveform should resonate down as close to 0V as possible - which is why you get a current pulse to discharge the remnant voltage.

Ciao, Tim

 

Without a schematic we can't even guess.

Here's the schematic:

The waveform certainly looks characteristic of a class E waveform

But the voltage and current are in phase and this causes a great dissipation on the transistor is not it? Do not you think that this is contrary to the class-E?

 

The current waveform you display appears normal, depending on circuit and parasitic component values, and where the current is being measured. Note that you identify the current as the power source feed current, not the FET current. The current flowing during the FET off time is the capacitive current due to the parasitic FET effective drain source capacitance (Cds + Cdg) and the voltage waveform.

Tuning the circuit would involve adjusting the frequency, C100, and the resonant load circuit. The circuit doesn't show a resistive load part, or is that attached to J5?

The losses in the circuit comprise resistive losses and energy lost due to charging/discharging capacitances. You need to differentiate between the amount of current through resistances, versus capacitive currents, to determine losses.

 

Note that you identify the current as the power source feed current, not the FET current.

Your words helped me understand where was the mistake. Do not take the current in the right place, placing the current probe below the resistor I got the new chart:

Now I think it goes well what do you think?

I will mention you in the acknowledgments of my thesis; D

 

I did an M.Sc on Clas E dc/dc conversion back in the early 80's so I've got half a chance of understanding what's happening. Remember i = C dV/dt, as it helps explain a lot of the current waveform. You're lucky nowadays, I had to look at 5 metre long stretched out line-printer plots for my waveform sims. Don't forget the FET capacitances are non-linear with voltage - especially Cdg. Maybe the FET model can be internally probed. Or you could probably set up a copy circuit in the sim which represents the FET resistive and capacitive elements - transfer the drain voltage waveform into the copy circuit - then probe just the resistive element to show the 'classic' current waveform.

Ciao, Tim