Hi there!
I have been studying the schematic attached with much confusion. At the input stage I am seeing VB applying 4.5v DC offset to the Op Amp through a 1M resistor.
Surely the voltage drop across this resistor would mean the Op amp wouldn't receive 4.5v bias?
I Understand the 1M resistor sends the input to a default state when nothing is connected and I understand that the op amp needs 4.5v DC to allow full swing between 9 and 0v, but the way it is applied in this schem is confusing me.
Can anyone help?
I have been studying the schematic attached with much confusion. At the input stage I am seeing VB applying 4.5v DC offset to the Op Amp through a 1M resistor.
Surely the voltage drop across this resistor would mean the Op amp wouldn't receive 4.5v bias?
I Understand the 1M resistor sends the input to a default state when nothing is connected and I understand that the op amp needs 4.5v DC to allow full swing between 9 and 0v, but the way it is applied in this schem is confusing me.
Can anyone help?
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