Sine to square wave conversion at 275 kHz problem

Thread Starter

Chris Wilson

Joined Dec 2, 2011
14
Sine to square wave conversion at 275kHz?
I built this circuit to try and turn the sine wave output from the 0 dBm Drive output socket at 275.1kHz of my Kenwood TS-590S transceiver, into a square wave so it would drive the input of the Class D amplifier also shown in schematic form. I usually drive the amp with the CLK0 output of the Si5351A synthesiser in a QRP Labs U3S used as an exciter on LF. This works fine, but the U3S has push button set up so resetting modes is a chore. The amp divides the signal by two as if feeds the FET driver IC and the resulting output frequency is 137.550kHz.

I built the circuit in the .gif below, but as it stood the bottoms of the waveforms were rounded. I tried using the same resistor values top and bottom (3.6k) on the bases of the transistors and the wave squared up, but the shape and 50 / 50 mark space ratio is very voltage dependent (the squarer voltage supply, that is). What considerations decide the top and bottom resistor values and how should they affect the square wave produced? Any tips for this please? I am pretty new to all this at a home brew level so please keep it very simple, thanks
BTW the amp does have plenty of decoupling caps not shown in the schematic right on the IC power pins!

input_Chris Wilson.jpg
http://www.chriswilson.tv/squarer/input.jpg

output_Chris Wilson.jpg
http://www.chriswilson.tv/squarer/output.jpg

device_Chris Wilson.jpg
http://www.chriswilson.tv/squarer/device.jpg

diffsqr_Chris Wilson.gif
http://www.chriswilson.tv/squarer/diffsqr.gif

amp-less-surplus-controls_Chris Wilson.jpg
http://www.chriswilson.tv/amp-less-surplus-controls.jpg
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Alec_t

Joined Sep 17, 2013
11,324
A perfect square wave would require an amplifier with an infinite bandwidth. That doesn't happen in the real world. There will always be stray capacitance and inductance (particularly with breadboard use) and transistor limitations which will detract from the ideal and distort the wave shape.
 

Alec_t

Joined Sep 17, 2013
11,324
CMOS gate approach -
Squarer.PNG
Where was the second waveform shown in post #1 measured? It's the waveform you would expect at the transistor emitters.
 
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danadak

Joined Mar 10, 2018
4,057
The issues that have to be dealt with using CMOS gate approach -

1) Strong T and V dependence of bias point on T
2) Device to device variation
3) Asymmetrical switching times on NMOS and PMOS transistors
in totem pole contributing to duty cycle variation.

Regards, Dana.
 

AnalogKid

Joined Aug 1, 2013
8,468
I built the circuit in the .gif below, but as it stood the bottoms of the waveforms were rounded.
That's because the bias point, or trip point of the comparator is too low. The period of time the 2nd transistor is off is so short that the output barely has time to reach the lower rail before it is yanked high again. Adjust one of the four resistors to get an output closer to 50/50%, and the bottoms will be flatter.

Another issue is the circuit's relatively low gain, leading to slow output transition speeds. The circuit is one emitter follower and one saturating transistor that is not overdriven into "hard" saturation.

Also, while the transistor's gain and low output impedance makes the output rising edge faster than the input sinewave edge, the falling edge is caused by nothing more than the 270 ohm resistor pulling down the load while it also discharges some of the transistor's stored charge; the output is driven high but wanders low. The solution is something with a totem-pole output and actively moves current in both directions and has a more nearly symmetrical, and lower, output impedance.

ak
 

Thread Starter

Chris Wilson

Joined Dec 2, 2011
14
CMOS gate approach -
View attachment 159574
Where was the second waveform shown in post #1 measured? It's the waveform you would expect at the transistor emitters.
Many thanks for the very detailed and helpful replies, this is where I am at the moment utilising bits I have to hand.


It was at the junction of the 270 Ohm resistor and the collector of the second transistor, where the schematic shows square wave out. I added a twenty turn pot in place of the first 3.3k resistor and by adjustment squared up the output, but I hadn't enough drive from the transceiver, so needed to add a broad band amp before the circuit.

This led me to try using a 4069 which appears to work well,
and it gave a decent looking square wave straight away, but the best waveform shape comes with 7V or even better 9V on its power pins. I have to sheepishly admit that i am not sure whether a 7V or 9V peak to peak square wave into a 74F74 is too high. The spec sheet for the 74F74 says absolute max of 7V DC. Is a P to P of 7v or 9V within its limits? I am thinking a plus and minus swing of at worst 4.5V either side of zero, so well within the 74F74's input limit, or am I being thick?

The other concern is the amp has spurious output noise when the exciter is not running. It is noise being received on the 4096 input pin, but I suspect that will disappear when built properly with ground plane and co-ax leads etcetera, unless there's other trickery to quell it needed?

I attach the schematic and the resultant output waveform with around 275kHz sine on the input pin (no preamp needed) and 9V on the 4069 power pins. 4069-9v.jpg 4069-squarer.jpg
 
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AnalogKid

Joined Aug 1, 2013
8,468
7 V is too high. Don't confuse absolute ratings with typical operating conditions. 74F series logic is one of the bipolar TTL families. It expects to run on 5.0 V and all signals in and out are less than that. An input logic high signal should be greater than 2.4 V. An input logic low signal must be less than 0.8 V. The actual transition level is around 1.8 V for standard TTL; don't remember what it is for F.

TTL has a relatively low input impedance.

https://en.wikipedia.org/wiki/Transistor–transistor_logic#Sub-types

ak
 
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