Hello there AAC!!!

end of term time is creeping up, Final assignments due in..

I have a couple of questions regarding the attached image.

I am creating a 4-bit parity circuit. The image is of a XOR gate in NAND. I have to prove that the configuration ends up with XOR function.

So the question arises..

1. Have i correctly shown the processes involved?

2. How do i simplify the final outcome so i can compare it with the XOR?

(for those of you who cant download the image (for whatever reason) here is what i ended up with)
______________
______________
____ ____
A.(A.B) . B (A.B)

reads

NOT NOT A AND NOT (A AND B) AND B AND NOT (A AND B)

in advance, Thank you so much Im really confused by this!

KG87

 

I thought i'd bump since others got a faster result that way.

Please help!

 

Here's one way.

 

Thank you so much.. I can finally get this Under wraps!

seriously,

THANKS