Can you eyeball any errors. Any concerns when into say 100kHz area? There will be hefty caps between +/gnd and -/gnd, etc.
Q1 and Q2 will have identical gate charge and rise time specs (or darn near identical). Q3 is the drive stage for Q1 Q2

 

I would be using a Totem-pole driver stage for the mosfets, instead of a single resistor and fet.

 

I would be using a Totem-pole driver stage for the mosfets, instead of a single resistor and fet.

but why? doesn't the one FET provide source and sink of charge for both power FETs?

 

but why? doesn't the one FET provide source and sink of charge for both power FETs?

No. The fet only provides the sink, the resistor provides the source. You would need very low value resistor which would mean huge power dissipation in that resistor in order to get the switching time good enough.
Second thing is, during the transistion between gate low and high (and the other direction as well) both main transistors will be on at the same time, which usually leads to magic smoke escaping and nice visual effects.
You don´t say what your voltage is, or what the actual purpose of the circuit is, so it is quite hard to recommend a solution. If your duty cycle never is 100% I would use two N fets and a dedicated gate driver like IR2110. If not, then you need to find a gate driver that can do that, or use a driving scheme with dead time and shoot-through prevention.

 

No. The MOSFET Q3 pulls the gates of both output to ground but only the resistor puls the gates towards the positive rail. You also need to consider that the supply voltage (The sum of the positive and negative voltages) must be less than the maximum gate source of the MOSFETs. The input square wave must be referenced to the negative supply rail. (Not the centre tap on the mains transformer secondary.)

Les.

 

It's only 12vdc ~100A, creating a simply high freq coil heater for steel parts. But instead of using a tank circuit I was looking at FETs.
An H bridge would also work, but I am using only two power FETs, not 4 in H.
Duty cycle fixed at 50%.

So yes, I see where bjt totem would work nicely.

 

I think that there is a reason why everyone uses a tank circuit, instead of driving the coil directly.
With a tank circuit, the fets only conduct the average current proportional to the heat going into the heated piece, and you switch them with zero volts across which is the ideal for them.
Without a tank you get much higher currents and switching at times where there is still a high voltage across the fets between one opening and the other closing, which has a huge impact on choice of fet ratings and switching losses.

I am not trying to discourage you, but I suggest you first get your gate driving circuit in perfect order, and then you compare for yourself your efficiency with and without a tank capacitor.

Or, without burning parts, go download LTspice for free, simulate the circuit with perfect gate drive and dead time and everything, check what the voltage and current is at the fets and what is the power dissipation, and decide for yourself.

 

so look now, the driver pair Q3 Q4 now contain delay feature, Q1 Q2 are now fast off, delay on by R1 R2, this removes the badness of Q1 Q2 on/on issue. R1 R2 (50Ω) provide some dwell time for gate charge to move during the off-to-on transition. i am not sure yet if this on dwell time can be timed to mag field collapse (that might be beneficial)? 100A FETs with Rds ~4mΩ are ez to find, so at 100A this is ~40watt each, but at 50% duty cycle just ~40watt total (a tad more for linear zone heat). not too bad. now need to find matching pairs. i suspect the key specs are gate charge & Miller plateau, and Rds ?

i have LTspice, just not fluent with it. anyone care to build this ckt. 12v60Hz feeding the rectifier, load is ~0.5mH with 0.001 Ω R, add in ~100Ω series to limit the current, lets see how they turn on/off.

i suspect it should behave like this when i get it into LTspice
red for Q1 , green for Q2, "slow" to full on then hard off before the other comes on "slow"

 

i am building it in LTspice. i used to work out of NI Multisim, hence why LT is a tad rusty for me, but, it took me just ~1hr of playing around with the latest version and its fairly simple.

 

Try this simple ciruit
https://forum.allaboutcircuits.com/threads/self-oscillator-circuit-push-pull-mosfet.73952/
Or google ZVS mazzilli

 

i made LT sim, it seems to work (attached)
this is crude sim, driver fet gates being driven by a AC source. M3 M4 will conduct at the same time, this was not intended, but it doesnt hurt M1 M2 operation. i tried 60Hz and 20kHz for the AC drive, and both appear stable (in terms of raw switching). fet's in linear zone still tbd, etc. note that this ckt was using very small inductor.

 

Please, PLEASE don´t ever make such a horibble mess of a schematic again. Here I redrew it so that I can at least look at it and see what goes where.

 

Please, PLEASE don´t ever make such a horibble mess of a schematic again. Here I redrew it so that I can at least look at it and see what goes where.

sure, i will try

 

well, the Id on power fet doesnt make sense to me. it should conduct in one direction only. disconnect one fet from inductor and we'll see nasty kV kickback. not sure why i dont see it when both fets are connected to the inductor. if the fets are both off for short period of time then we should see this flyback V on every cycle, but LT does not show it. reverse Id could be from flyback breaking through, but the Id is symmetrical from graph and i would not expect that. notice there is no flat in L amps, this ckt was 1kHz with 1mH, so i suspect the coil mag field has not fully collapsed while M1 M2 flip flop?

 

Don't forget about the body diodes in the fets. They are most likely conducting and dumping the inductor current back into the power supplies.

 

this with 20u inductor. when L amps turns off i see a normal voltage spike (aka flyback) with some ringing, that seems normal, but how does that short current burst happen to M4 in the opposite direction? the more inductance i use the worse it gets. this spike occurs right at the point the opposite FET turns off. i initially thought the flyback was so high that it punched through the FET but LT v probe does not show that. however, if you run the model with just one FET on the load inductor (1m) LT v probe shows kV spike levels.

so, this has me a tad baffled.

Don't forget about the body diodes in the fets. They are most likely conducting and dumping the inductor current back into the power supplies.

ah, but shouldnt i see a higher V than ~12v ?

let me try placing a diode under each drain to block return amps.

edit: even with diodes the voltage rises very high (540v) but didnt reach diode 800v reverse v rating, FET still shows some reverse current. let me snub it with a zener.

 

ah, but shouldnt i see a higher V than ~12v ?

Body diodes behaviours just like an ordinary diode connected between drain-source.

This means that the voltage at the inductor will never be larger than 12V + Vd = 12V + 0.7V = 12.7V or -12.7V for the N chanel MOSFET.

even with diodes the voltage rises very high (540v) but didnt reach diode 800v reverse v rating, FET still shows some reverse current. let me snub it with a zener.

Can you uplaod the LTspice file?

 

Can you uplaod the LTspice file?

attached