Hi,
I have to design a small simple look-up table with
Word length 8-bit
and there are 4 words,

How to make circuit in cadence in MOSFET level (for smaller area, without using FPGA) so that we can read multiple times after programmed the bits once.
my objective is to write once and read the location based on the input multiple times.

thanks

-Safiya

 

What type of memory element are you planning to use?

 

This looks like it is probably some type of school assignment. Is it? If so, we can move it to Homework Help were it will get more of the type of attention you would be looking for.

 

What type of memory element are you planning to use?

my contents are like this , it probably be stored as constants and read multiple times depending on the input
1 0.1
2 0.01
3 0.1

 

This looks like it is probably some type of school assignment. Is it? If so, we can move it to Homework Help were it will get more of the type of attention you would be looking for.

its not a school assignment it is BS level assignment

 

its not a school assignment it is BS level assignment

How is a BS level assignment not a school assignment?

Are you getting any kind of academic credit for this?

 

my contents are like this , it probably be stored as constants and read multiple times depending on the input
1 0.1
2 0.01
3 0.1

Not what I was asking, although it brings up another question: What is the representation of the information you are going to store? You said that your data fields were 8-bits. How are you going to store values like 0.1 and 0.01 in that 8-bit field?

But what I was asking is what kind of memory element are you going to you? DRAM? SRAM? What topology? Cross-coupled inverters? Contention-free logic? What?

 

If it is assumed that there is a processor behind all this then you could use a lookup table stored in processor memory and then only store indexes into the table, then you would be storing much simpler values. It really comes down to the higher level requirement, taken out of context there are many solutions.

 

It sounds like the assignment is to design a CMOS circuit and do the layout for it in Cadence.

 

Not what I was asking, although it brings up another question: What is the representation of the information you are going to store? You said that your data fields were 8-bits. How are you going to store values like 0.1 and 0.01 in that 8-bit field?

But what I was asking is what kind of memory element are you going to you? DRAM? SRAM? What topology? Cross-coupled inverters? Contention-free logic? What?

I want to store decimal -0.1 and -0.01

How is a BS level assignment not a school assignment?

Are you getting any kind of academic credit for this?

No , ,, nothing is related with credit for this kind of simple ckts

 

Not what I was asking, although it brings up another question: What is the representation of the information you are going to store? You said that your data fields were 8-bits. How are you going to store values like 0.1 and 0.01 in that 8-bit field?

But what I was asking is what kind of memory element are you going to you? DRAM? SRAM? What topology? Cross-coupled inverters? Contention-free logic? What?

I am novice to memory design , can i store decimal (-0.1) in 8-bit word length or shud i need more bits , it is signed too. which memory will take less area ,
before this i have analog part and ADC.
thanks

 

Actually, you cannot represent decimal -0.1 in binary without losing precision. Nevertheless, when did the jump from storing 8bit integers to storing signed real numbers happen?
Whatever the answer to that is, you can esasily divide this into two tasks, one being storage of the four 8bit words, the other one coding and decoding your signed real numbers into 8bit representation.

 

Actually, you cannot represent decimal -0.1 in binary without losing precision. Nevertheless, when did the jump from storing 8bit integers to storing signed real numbers happen?
Whatever the answer to that is, you can esasily divide this into two tasks, one being storage of the four 8bit words, the other one coding and decoding your signed real numbers into 8bit representation.

Yes there is no jump, alternatively
if the input is ,1 the memory should out the stored -0.1,
if the input is ,2 the memory should out the stored -0.01,
if the input is ,3 the memory should out the stored -0.3,

 

Yes there is no jump, alternatively
if the input is ,1 the memory should out the stored -0.1,
if the input is ,2 the memory should out the stored -0.01,
if the input is ,3 the memory should out the stored -0.3,

I have no idea what that is supposed to mean. Can you be a bit more concrete about what goes in an what goes out?

 

its not a school assignment it is BS level assignment

Just to be clear. Does BS stand for Bachelor of Science, the degree you would get after completing a four year course at a University? If not could you let us know what it does stand for because we are in the dark.

 

I want to store decimal -0.1 and -0.01

You need to be very clear and specific about the data you are storing. What are the range of values you need to be able to store and what is the resolution. That will dictate the options for how you will represent the data and whether 8-bits is sufficient.

No , ,, nothing is related with credit for this kind of simple ckts

Then why are you doing it? What happens if you don't do it?

What is your major? What level are you presently at? What course is this for? That information will help us know what is reasonable to expect for your background and what subjects we should probably assume you have not seen yet.

 

I'm not particularly concerned with what it is for. Hopefully you'll learn either way. Here is one way to do a memory cell, if you have control of transistor dimensions.

This needs 6 transistors, two for each inverter, and two for the input. It's important not to have A=0 and B=1 at the same time, of course. At least, not for more than a few nanoseconds. The idea is that the top inverter is very weak, and you overpower it to force the desired value into the memory cell.

Another way to do this is to have a transmission gate at the input of the big inverter instead of the two transistors. But then, you need to make sure that your driving logic signal is strong enough to overcome the small inverter through that transmission gate. Instead of using a transmission gate, you might use just a pass transistor (n-type), and it might be lower area. But with such a small memory, it might not be worth trying to save every last square micron.

If you do NOT have control of transistor dimensions, then you'll have to basically do a latch or flip-flop from combinational logic. Kind of expensive in terms of area.

 

You can also use NFETs for your input transistors and then two cross-coupled inverters with weak PFETs. Since NFETs are inherently stronger then PFETs, this often allows you to use minimum dimensions on everything.