The circuit is a two-wire interface where the voltage across R_LOAD should be proportional to the current drawn by the VCCS plus the DC bias current from the IC Q-currents.

Without the diode isolating the signal terminal from the bypass capacitance, I simply cannot achieve the desired bandwidth due to the effective LPF created by C1 and R_LOAD. The problem is that with the diode, although the VCCS current is not attenuated, it is also not identifiable by measuring the voltage drop across R_LOAD. This is due to the "bias" current fluctuating as the bypass capacitor is charged when the diode is "on" (caused when VCCS draws a minimum current), causing a superposition of these two currents across R_LOAD.

I've hit a snag and hope that there are some suggestions regarding the isolation of the signal path from the large bypass capacitance (C1) necessary for the ICs in this circuit to function properly. Any help is appreciated.

 

C1 can likely be much smaller while still allowing proper circuit operation, perhaps 1μF or less. Have you tried smaller values?

Alternately, to provide isolation, you could add a voltage regulator to power the ICs which would then draw a constant current from the source, independent of the signal level.

 

Why are you interested in having Vcc current across the load? Unless there is a really good reason, isolate the load from Vcc. Also isolate the final stage from the upstream ones.

 

It looks like you are trying to create something similar to a 4-20ma transmitter.

I think the problem is that the return current for the circuit is outside the loop that R1 measures. OA2 cannot compensate for currents outside its feedback loop.

You need to return your ground current to the node on the top side of R1, not the bottom. This will then allow OA2 to compensate the whole circuit properly.

A quick google search found this page:

http://gadgetsinside.wordpress.com/...20-ma-current-loop-measuring-circuits-basics/

Scroll down to where it says "2 wire transmitter electronics". You may be able to adapt what he did to what you are trying to do.

 

I think R1 is correct. Assuming 2V at the input of the op-amp, that would give 20mA for the output. Still I don't think you want to use V4 across RL as you are doing. Supply VCC to the amps as a direct connection. Use a resistor in parallel with the final output stage if you want a programmed quiescent current across RL.

 

Short D1 and R_LOAD and make R1 your new R_LOAD, perhaps?

 

It would appear the circuitry on the left is the transmitter, and the resistor and voltage source on the right is the receiver and single power source for a 4-20mA current loop. Thus I think my recommendation stands.

A voltage regulator would isolate all the circuitry on the left (expect for Q1's collector) from the control loop. The DC bias from the Bandgap Reference is adjusted so that the total quiescent loop current, including the power drawn by the circuit, is 4mA (obviously the circuitry must draw less than 4mA total). Q1 then varies the loop current in response to the V1 signal. The signal is measured as a voltage across R_LOAD.

 

As joeyd999 has assumed, this design has to be a two-wire interface. Therefore the Q-current must pass through the load resistor. Supplying VCC to the ICs is not an option as this would require a three-wire interface.

@crutschow - A 1uF capacitor (without the diode) gives me a bandwidth of ~2-3kHz. I'm seeking upwards of 50kHz. With 100 Ohm load resistor the effective bypass capacitance seen by the VCCS can be no larger than ~10nF. Obviously 10nF is not enough for the ICs to work properly (without substantial noise).

@joeyd999 - I understand your concern in the ground current which should generally be compensated for. It just so happens that the Q current is practically DC, even while the gain stage and VCCS op amps are working. I suspect you're referring to something similar to this setup?

I feel that the reference must still be grounded at true ground, otherwise V_ref will not remain fixed. Unfortunately this still does not solve the isolation problem for increasing the circuit's bandwidth.

 

crutschow - Valid suggestion, the main problem with this is that the final circuit should be rated at +175 C. It has been difficult enough to find HT ICs with low temperature equivalents for testing, and the only HT voltage regulator I've found is the REF5025, which acts as my reference volage for the gain stage with a V_ref of 2.5V. My options are limited, so if you can suggest any components please let me know.

EDIT: Something with a ~10V output, that doesn't cost $600
http://www.digikey.com/product-detail/en/HTPLREG10TC/HTPLREG10TC-ND/2046728

 

...It just so happens that the Q current is practically DC....

Yes, the Q current of the amplifiers....but not the AC current through C1. That is the current that is causing your bandwidth problem. Your new circuit *still* has the C1 current outside the regulated loop, so you should still have the same problem.

Like Crutshow said, you may be able to add a voltage regulator at the front end to stabilize the DC voltage across C1. Or, you can just put C1 inside the loop with everything else (and make sure OA2 has the bandwidth necessary to make the corrections at your max frequency).

FYI, I didn't spend a lot of time analyzing your circuit. These are thoughts that just popped into my head at first glance. Even a stopped clock is right twice a day...

 

Hmm, I definitely see what you mean now. I will try this out, keep my fingers crossed, and let you know my results. The only disadvantage that I see in this is that the R1 voltage will now be V_R1 = R*(Q_A1 + Q_A2 + VCCS). If all that is available to me is a 2.5 V_Ref, and I wish to achieve a 2V span (4.5V <--> 0.5V signal) R would need to be reduced to less than 100Ohm given that Q_A1 + Q_A2 ~= 10mA.

 

Hmm, I definitely see what you mean now. I will try this out, keep my fingers crossed, and let you know my results. The only disadvantage that I see in this is that the R1 voltage will now be V_R1 = R*(Q_A1 + Q_A2 + VCCS). If all that is available to me is a 2.5 V_Ref, and I wish to achieve a 2V span (4.5V <--> 0.5V signal) R would need to be reduced to less than 100Ohm given that Q_A1 + Q_A2 ~= 10mA.

I don't understand what you are getting at. Your total voltage available to power your circuit is the Vce of Q1, not the voltage drop across R1. With a 20V source voltage at your receiver, you should have at least 16volts or more to power the circuit. Am I missing something?

 

Thinking some more about this on my drive home from the office:

C1, that 20uF cap, is going to kill you no matter what you try to do -- unless you stabilize it's voltage.

Think of it this way: Your rail voltage is going to vary up to +/- 2V at the frequency of the signal source. Something is going to have to deliver the A/C current through that cap. If the cap is outside the servo, the loop will have to provide the current causing the high freq attenuation you are seeing. Inside the servo, Q1 will will provide the charge/discharge currents, but that will cause large voltage swings and excessive power dissipation. And, assuming the servo can keep up, will cause the cap to appear non-existent.

If you need to filter the input voltage to the reference, then you are going to have to regulate first. *And* you cannot use a low-dropout regulator. Those *require* an input cap for stabilization, I believe. You'll need to use something with a standard pass-transistor topology.

Again, I may be wrong.

 

I'm impressed that this is going to operate at 175C. Did I read that correctly?

 

I see what you mean and I'll look into the Linear Regulator as a solution.

Let me rephrase what I said in my previous post. The OAs are grounded at the feedback terminal (V_Sense) such that their Q-current is compensated for by the VCCS. But correct me if I'm wrong, this also sets a lower limit on the allowable signal voltage span since the Q-current, being roughly ~10mA, will produce 1V across the sense resistor of 100 Ohms at all times. So for a V_Signal < 1V, at best, OA2's output will be driven to ~1V, shutting off the NPN, but a voltage < 1V cannot be produced at V_Sense.

In the schematic shown below, the linear regulator is also referenced by V_Sense. So if it were to be a 5V regulator, Vcc, measured relative to the true ground, will oscillate with a voltage of (V_Sense + 5V). This does not cause a problem if the OAs wish to drive their outputs higher than V_Sense, but I'm having trouble convincing myself that OA1 will accurately/instantaneously decrease it's output voltage in response to a stimulus seeing as it's ground terminal is at V_Sense.

Is R3 in the schematic below actually compensating for the effects that I've discussed?

http://gadgetsinside.wordpress.com/...20-ma-current-loop-measuring-circuits-basics/

@T_N_K - I've tracked down components with HT equivalents so that I can first test up to +125. That is why my design is so specific. Provided that the sense resistor has a very low temperature coefficient, with correct feedback and a reliable reference voltage the signal current should be resilient to temperature. These are my assumptions of course, I may be proven wrong... such is the learning process.

 

crutschow - Valid suggestion, the main problem with this is that the final circuit should be rated at +175 C. It has been difficult enough to find HT ICs with low temperature equivalents for testing, and the only HT voltage regulator I've found is the REF5025, which acts as my reference volage for the gain stage with a V_ref of 2.5V. My options are limited, so if you can suggest any components please let me know.

EDIT: Something with a ~10V output, that doesn't cost $600
http://www.digikey.com/product-detail/en/HTPLREG10TC/HTPLREG10TC-ND/2046728

How about one of these? They're still expensive, but less than a tenth of your referenced cost. Devices rated for 175°C operation are not common or cheap.

 

How about one of these? They're still expensive, but less than a tenth of your referenced cost. Devices rated for 175°C operation are not common or cheap.

Seems like this could work. It was mentioned earlier that an LDO would not work for this application since they require an input capacitance but the data sheet specifies that it is recommended but not required. I will have to search for a low temp equivalent or non-LDO regulator.

In the meantime, I am still perplexed as to how the op amps in the previously posted schematics can have their grounds connected to a voltage terminal which they have direction influence over, yet they should function seamlessly.

 

In the meantime, I am still perplexed as to how the op amps in the previously posted schematics can have their grounds connected to a voltage terminal which they have direction influence over, yet they should function seamlessly.

I guess the principal requirement for correct op-amp control would be that the input voltage at U1B pin 5 would need to be within the common mode range of the op-amp. Op-amps with common mode range including supply common [single supply mode] are readily available.

I would imagine to set this condition [i.e. U1B pin 5 input at supply common] one would then have the relationship

\(I_{loop}=\({\frac{R_3+R_{sense}}{R_{sense}}}\)I_3\)

where I3 is the current in R3 - or that component of the loop current which bypasses Rsense. I'm assuming D1 isn't conducting under normal operating conditions.

 

Apropos my previous post I would refer you to a Burr Brown IC device [XTR117] which is specifically designed as a loop powered transmitter. The device schematic design approach is pertinent to the discussion rather than itself being applicable to your requirement. Probably not recommended for 175C operation.

 

In a configuration such as this...

What would cause a resonance of the supply current (current through R1, which should be directly proportional to the current drawn by the VCCS) due to an interaction with the regulator and its output bypass capacitance?

I have tested a similar setup and found that with a 1uF output bypass capacitance there was a resonant peak of the transfer function of I(R1)/I(R2) at about 30kHz. Reducing the capacitance to 220nF resolved the problem, I assume by increasing the resonant frequency. But it is not clear to me where an inductive equivalence would appear in this circuit to create this response.

I've read some information on regulators (LDO/Pass) and they mention a "carrot" in the regulator output impedance response with respect to frequency. Could the observation I've mentioned be related to this characteristic?