Hi all, few questions about thermal vias for dissipating heat to a large copper area below a SiC Schottky diode.
In a previous design I used 0.3mm vias spaced apart 0.8mm, with no annular ring and direct connect. The dissipation was quite a bit more than I expected.
I am redesigning the board and revisiting the topic of thermal management using vias. I am unsure whether my thermal vias should have any kind of annular ring or just be a 0.3mm copper plated hole. I am working with the assumption that annular rings are for a good connection to a copper trace, but I am not so sure whether that matters if a 0.3mm is directly connected to a large copper plane, and whether any annular ring would improve thermal impedance or solderability. Some resources such as https://www.protoexpress.com/blog/dont-let-annular-rings-drive-you-crazy/ state that to avoid breakout, annular rings should be >8mil, but again this does not directly refer to thermal vias connecting to a large copper area on a different layer. I currently have a via that is 0.3mm in diameter, with a minimum 8mil (0.2032mm) annular ring, which looks like this:

References online typically are not clear on this - and often the vias don't seem to have any annular rings from photos that I have seen. But to understand the effect on thermal impedance could be interesting....
Best,SIC
In a previous design I used 0.3mm vias spaced apart 0.8mm, with no annular ring and direct connect. The dissipation was quite a bit more than I expected.
I am redesigning the board and revisiting the topic of thermal management using vias. I am unsure whether my thermal vias should have any kind of annular ring or just be a 0.3mm copper plated hole. I am working with the assumption that annular rings are for a good connection to a copper trace, but I am not so sure whether that matters if a 0.3mm is directly connected to a large copper plane, and whether any annular ring would improve thermal impedance or solderability. Some resources such as https://www.protoexpress.com/blog/dont-let-annular-rings-drive-you-crazy/ state that to avoid breakout, annular rings should be >8mil, but again this does not directly refer to thermal vias connecting to a large copper area on a different layer. I currently have a via that is 0.3mm in diameter, with a minimum 8mil (0.2032mm) annular ring, which looks like this:

References online typically are not clear on this - and often the vias don't seem to have any annular rings from photos that I have seen. But to understand the effect on thermal impedance could be interesting....
Best,SIC