Should logic gates have a pull down resistor

Thread Starter

MikeJacobs

Joined Dec 7, 2019
118
I know this typically depends on if its ttl or CMOS

But to simplify the question, is there anything wrong with putting a pull down on a cmos chip?
I know its needed on a ttyl part but if you use one on cmos is it bad?

Also, what is a good value for a pulldown for say a 4-5V part.

100k?

say you have a simple or / and gate
Is there any badness from putting pulldowns on both the inputs and the outputs if the output is driving say a bjt?
 

Papabravo

Joined Feb 24, 2006
13,735
Pulldowns on TTL are a bad business because TTL inputs are the emitters of multi emitter transistors and they source current. A large enough resistor on a TTL input will allow the input to float up to and beyond what is considered a logic '0'. CMOS does not suffer the same problem. Pulldowns for CMOS can be in the 22K to 47K range
 

Thread Starter

MikeJacobs

Joined Dec 7, 2019
118
Pulldowns on TTL are a bad business because TTL inputs are the emitters of multi emitter transistors and they source current. A large enough resistor on a TTL input will allow the input to float up to and beyond what is considered a logic '0'. CMOS does not suffer the same problem. Pulldowns for CMOS can be in the 22K to 47K range
Thanks

so how do you pull down a ttl?

any reason I cant use 100k on cmos If that is what I have?
 

MrChips

Joined Oct 2, 2009
21,133
You are attempting to make a general statement where maybe none exists.

Firstly, we will assume that you are referring to inputs to any digital logic circuit. In particular, we assume that you are referring to unused inputs to any digital logic.

Independent of whether the logic is designed using TTL (BJT) or CMOS, the same rule applies. All unused inputs should be connected to a valid logic level, logic LOW or logic HIGH, depending on the function of the input pin.

If input pins are being driven by valid logic levels in both states, no pull-up or pull-down resistor is required.

If the input pin is not being driven by a valid logic level in either state, then a pull-up or pull-down resistor can be used to set the input to a valid logic state. The value of the pull-up or pull-down resistor will depend on circuit configuration and LOW and HIGH input current parameters of the input pin. Input current specifications are provided in the manufacturer's device datasheet.
 

Thread Starter

MikeJacobs

Joined Dec 7, 2019
118
Can you post a circuit diagram showing your specific application?
Don't have a specific application just learning.
But for the sake of it
Say you have an Arduino tied to the inputs of an AND gate

No pull down required your saying? Assuming the Arduino or whatever flavor MCU or FPGA is doing it for us internally?

No say you took that same and gate and were powering the base of a BJT. You would want a pull down there correct?
 

WBahn

Joined Mar 31, 2012
25,762
Pulldowns on TTL are a bad business because TTL inputs are the emitters of multi emitter transistors and they source current. A large enough resistor on a TTL input will allow the input to float up to and beyond what is considered a logic '0'. CMOS does not suffer the same problem. Pulldowns for CMOS can be in the 22K to 47K range
Certainly the ideal situation is to design your TTL logic so that unconnected inputs should be pulled HI so that the internal behavior of the TTL input stage will make this happen and also to reduce the quiescent power consumption. Even then it is often prudent to provide an external pullup resistor since the normal behavior often doesn't have a lot of noise immunity.

But there are going to be times when you need an unconnected TTL input to be pulled LO and using a pulldown resistor is a perfectly valid way to do this. But you have to design it with the spec sheet in mind. The simplest way is to first determine what value of resistance is needed to ensure that the input voltage is never above Vilmax (V input LO max) while sinking Iilmax. Then generally cut that value in half and don't use anything above that.
 

MrChips

Joined Oct 2, 2009
21,133
Don't have a specific application just learning.
But for the sake of it
Say you have an Arduino tied to the inputs of an AND gate

No pull down required your saying? Assuming the Arduino or whatever flavor MCU or FPGA is doing it for us internally?

No say you took that same and gate and were powering the base of a BJT. You would want a pull down there correct?
If a general purpose input-output pin (GPIO) of an MCU was configured as OUTPUT and was driving another device with a digital INPUT, TTL or CMOS, no pull-up or pull-down resistor is required, assuming that the output levels of the GPIO can satisfy the input requirements of the input.
 

Thread Starter

MikeJacobs

Joined Dec 7, 2019
118
Also, just to be clear, im talking about inputs that are dirven by something else. Either a simple toggle switch driving a gate or an MCU.

In most cased, I would almost always tie everything high or low if an unused input was the subject.

Speaking of which, what are the risks of driving a logic gate with a something simple like a toggle switch.
I am imagining debounce becomes an issue
 

MrChips

Joined Oct 2, 2009
21,133
Also, just to be clear, im talking about inputs that are dirven by something else. Either a simple toggle switch driving a gate or an MCU.

In most cased, I would almost always tie everything high or low if an unused input was the subject.

Speaking of which, what are the risks of driving a logic gate with a something simple like a toggle switch.
I am imagining debounce becomes an issue
Ok. You are throwing in two new situations that are different from the previous discussion.

1) A mechanical switch connected to a logic input needs a pull-up or pull-down resistor to satisfy logic input when the switch is in the NO (normally open) state. We can show you how to calculate the value of the required resistor. For this, we need to look at the data sheet of the device. This was alluded to by the member in post #7.

There are other situations not involving mechanical switches that also require pull-up or pull-down resistors.

2) Whether or not debounce of a mechanical switch is required depends on the application. Not all instances of switch usage require that the switch be debounced.
 

AnalogKid

Joined Aug 1, 2013
8,464
There are several different flavors of TTL (Standard TTL, LSTTL, Schottkey, Advanced Schottkey, etc.) and each has its own input current spec. For standard TTL, you must sink 1.6 mA of current out of an input to GND, and the maximum input voltage for a logic zero state is 0.8 V. With Ohm's Law, these combine for a maximum pull-down resistor value of 500 ohms. So 470 is iffy, 330 is better, and 220 is (was) very common. For LSTTL, I think the max is 1 K.

100 K for a CMOS pull-down will work, but that is a relatively high impedance and could allow for false inputs caused by radiated noise.

When driving an NPN bipolar transistor (emitter to GND) with a logic gate output, most logic families have a low enough logic 0 output voltage to turn off the transistor without a pull-down resistor to GND. If you want to add one, put it between the base and GND, not the gate output and GND.

When driving a logic gate with a mechanical switch, bounce is an issue only if the downstream circuits are sensitive to it. For example, if the switch is driving the clock input of an event counter, then flipping the switch could be seen as 20 events. OTOH, if the switch is driving a latch input, then latching the same data 20 times in a few milliseconds probably is not a problem because the latch outputs don't change after the first clock edge.

ak
 

Thread Starter

MikeJacobs

Joined Dec 7, 2019
118
Ok. You are throwing in two new situations that are different from the previous discussion.

1) A mechanical switch connected to a logic input needs a pull-up or pull-down resistor to satisfy logic input when the switch is in the NO (normally open) state. We can show you how to calculate the value of the required resistor. For this, we need to look at the data sheet of the device. This was alluded to by the member in post #7.

There are other situations not involving mechanical switches that also require pull-up or pull-down resistors.

2) Whether or not debounce of a mechanical switch is required depends on the application. Not all instances of switch usage require that the switch be debounced.
Thanks for all your input thus far

So back to my example from before

so you have a 2 input and gate. One side is a switch the other side is an Arduino
Lets assume its a cmos and gate

How do you calculate the pull down?

What about debouncing in that situation
 

Thread Starter

MikeJacobs

Joined Dec 7, 2019
118
When driving an NPN bipolar transistor (emitter to GND) with a logic gate output, most logic families have a low enough logic 0 output voltage to turn off the transistor without a pull-down resistor to GND. If you want to add one, put it between the base and GND, not the gate output and GND.
Thanks!
Just to clarify, your meaning after the base resistor. So out of the gate into RB our of RB then put the pull down to GND then continue to the base.
That is what I was planning
 

AnalogKid

Joined Aug 1, 2013
8,464
Yes. The resistor is there to limit the base current to a value that is safe for both the transistor and the logic gate output stage.

ak
 

Papabravo

Joined Feb 24, 2006
13,735
...
so how do you pull down a TTL input?
You use a small value resistor such that the voltage drop across it << 0.8V Let us say we are willing to have the input go up to but not exceed 0.35 V, as it sources a standard TTL load of 1.6 mA. So 0.35 V / 1.6 mA = 218 Ω, so maybe 180 Ω. That resistor will dissipate 461 μW with 1.6 mA flowing
 

djsfantasi

Joined Apr 11, 2010
6,427
Ok, just Wow!

This is a great example of a simple question that leads to a slew of additional questions.

Every post is valid. I’m really appreciative that we got as far as considering debounce.

It’s a great example of why we need a lot of detail. It’s necessary in order to answer the problem asked. And an example of how a poster needs to consider the entirety of their issue.
 

atferrari

Joined Jan 6, 2004
3,962
Ok, just Wow!

This is a great example of a simple question that leads to a slew of additional questions.

Every post is valid. I’m really appreciative that we got as far as considering debounce.

It’s a great example of why we need a lot of detail. It’s necessary in order to answer the problem asked. And an example of how a poster needs to consider the entirety of their issue.
Hola @djsfantasi

Is not easy to expect, from someone who is starting to learn on the matter, to cover in the OP, all the aspects. This thread reminded me the times when I started trying to understand digital techniques. I still recall well when, for a small circuit named Big Ben, supposed to generate a sound of sorts that did not work after being assembled by a friend and gave it to me, the guy at the counter told me "check the clock".

WTF, a clock inside!!, I said... go figure.
 

MrChips

Joined Oct 2, 2009
21,133
There are two ways to connect the switch, on the high side and on the low side.
High side and low side switch.jpg
With the high side switch, pressing S1 pulls the input HIGH while R1 pulls the input LOW when the switch is released.
The role of R1 is to sink the input current IIL and maintain a valid logic low voltage VIL. These parameters are found in the logic device's datasheet.
Calculate R1 = VIL / IIL. Use a lower resistance value to give you some headroom.

For example, typical specs for CMOS logic operating at Vcc = 5V show IIL = 1μA and VIL = 1V.
Hence R1 = 1V / 1μA = 1MΩ
Choose a resistor lower than this. Anything from 10k to 100kΩ would be suitable for R1 pull-down resistor.

For the low side switch, pressing S2 pulls the input LOW while R2 pulls the input HIGH when the switch is released. The calculation for R2 is similar to the previous calculation for R1. Use R2 = (Vcc - VIH) / IIH. Again, anything from 10k to 100kΩ would be suitable for R2 pull-up resistor.

There is a wide range of suitable resistor values with CMOS gates because of the low input currents (high impedance inputs).
With 7400 series logic the range is much more restricted and you have to pay closer attention to the datasheet specifications for the specific 7400 logic family, for example, 7400 vs 74LS00. A sample calculation was given in post #16, You will find that the value for a pull-up resistor is very different from the value for a pull-down resistor.
 
Top