I was working on an smps design using SG3524N but found out something confusing in the datssheet of the SG3524N. The datasheet shows that internally the two transistors will give output complemented to each other as shown.


But there is a design of flyback where both of the collector and emitter are shorted. Now suppose the first transistor is high and other is low, then the current will flow in the circuit using the first transistor, but in the other cycle the same will happen because now the second transistor is ON and the second one is OFF and current again flows due to the second one.

This shows that the current is continously flowing and there is no duty cycle generated. How is this working???Kindly help me in this confusion if I am understanding it wrong.

 

The outputs are not complementary, they are alternate.
Complementary would mean that when one was ON the other was OFF, and vice versa, which is not the case.
If you inspect the logic you will see that both transistors are gated OFF by both the oscillator and the comparator.
The oscillator gives the dead time signal (when both transistors are OFF).
The comparator produces the PWM signal: when the output of the error amplifier indicates that the output voltage is higher than the reference voltage, both transistor are OFF.
At other times the T (toggle) flip-flop allows each transistor to be ON alternately.

 

The outputs are not complementary, they are alternate.
Complementary would mean that when one was ON the other was OFF, and vice versa, which is not the case.
If you inspect the logic you will see that both transistors are gated OFF by both the oscillator and the comparator.
The oscillator gives the dead time signal (when both transistors are OFF).
The comparator produces the PWM signal: when the output of the error amplifier indicates that the output voltage is higher than the reference voltage, both transistor are OFF.
At other times the T (toggle) flip-flop allows each transistor to be ON alternately.

But basically if the pwm cycle is less than the threshold then it would continously give high. Meaning that we wount have a pwm voltage at the output as in case of other topology where the change in threshold changes the duty cycle. Here we just have turn ON and OFF no pwm....In TL494 we had a control pin that gave the control of using either parallel combination of bjts or seperate.
Kindly correect me if I am wrong

 

But basically if the pwm cycle is less than the threshold then it would continously give high. Meaning that we wount have a pwm voltage at the output as in case of other topology where the change in threshold changes the duty cycle. Here we just have turn ON and OFF no pwm....In TL494 we had a control pin that gave the control of using either parallel combination of bjts or seperate.
Kindly correect me if I am wrong

The dead time output from the oscillator will prevent it from being on all the time.
Or, if you want a maximum duty cycle of ~50%, then just use one output transistor.

 

The dead time output from the oscillator will prevent it from being on all the time.
Or, if you want a maximum duty cycle of ~50%, then just use one output transistor.

Right means its only the dead time that is prevents it else it will be high and low oscillating depneding on the compator input?