I understand the theory of what you're saying, it's just that we've built a bunch of these and haven't seen that failure yet, so I just want to make sure as much as possible that this failure can actually happen.

As you said that the fets are being tested, this is more of a reliability issue than a safety issue, right?

 

"... we've built a bunch of these ..."

Note that every simulation shown uses the same 0-10 V signal to switch both FETs. Is that what you are actually doing?

 

Thanks for the info. That's what I thought you were saying. I'm not sure I understand how leakage current varies with Vds if at all. If the lower transistor has lower leakage than the upper transistor, will it start to increase as the voltage between the two starts to float up? will the upper transistor leakage reduce as it's Vds gets smaller?

I understand the theory of what you're saying, it's just that we've built a bunch of these and haven't seen that failure yet, so I just want to make sure as much as possible that this failure can actually happen.

The leak is determined by the built-in diode (at low thresholds, a subthreshold current is added).Dependence is direct: more voltage - more current.Sometimes a leak is modeled by a resistor.In the model of the transistor, a resistor 10MOhm-300MOhm is placed parallel to the transistor.Usually, the more powerful the transistor, the lower the denomination.In addition, as the temperature increases, the leakage increases greatly.Look at the datasheet to your transistor.Usually the maximum leakage is given at two temperatures.

 

In a sort of "medium size" FET, the drain-source current with zero Vgs is typically something on the order of 1/4 of a milliamp maximum at 125 °C.

The issue with leakage is that the source of the upper FET could conceivably be raised to 28 volts if the upper FET were leaky and the lower one had no leakage. This would make Vgs of the upper FET -28 V with the gate driver output was at zero. Most power MOSFETs have an absolute maximum Vgs rating of ±20. In reality, many will withstand considerably higher, but that is not a risk I'd recommend for something that needs to work reliably. Leakage in the bottom FET is not an issue with regard to Vgs of either FET.

By adding a resistor in parallel with the lower FET, a guaranteed path for the upper's leakage current is created and thereby the maximum source voltage of the upper FET limited when it is nominally OFF. For example, assuming the lower FETs leakage is zero and the upper's is 250 µA, shunting the lower FET with 56k would keep the source of the upper FET at 14 volts (maximum). This would keep the gate-source voltage of the upper FET within allowable limits for any type with a maximum Vgs of ±20 V with 0 to 10 V from the gate driver circuit. This of course may increase the OFF current through the load.

The perhaps dubious advantage to this scheme is that you don't have to change the driver. I think I'd still prefer to directly limit Vgs of the upper FET with diode or zener clamp and a moderate resistance, probably no more than 5k, in series with the gate. Depending on just how that is done, it could form sufficient path for the D-S leakage.