Hi

I am trying to understand SPI configurations. Especially with regards to CKP, CKE and SMP. When do you choose 1 and not the other one. ie

1) For CKP when do you choose Clock Idle at High and not Clock Idle at Low?
2) For CKE when do you choose transmitt at falling edge and not transmitt at rising edge?
3) For SMP when do you choose sample at middle and not sample at end?

Or can you just choose a configuration as long as they are consistent throughout?

Thanks

 

Hi,
Look thru this SPI App pdf file.

E

 

Hi Eric,

Thanks. I have read that data sheet. I am not sure if you understand my question. I am not referring to how to set the configurations or what each setting means. Maybe you can provide your experience on choosing one over the other. Does it differ with devices? Or is it just a personal choice as long as you are consistent with the configuration throughout the program?

Cheers

 

hi umibuta,
For me just a personal choice, as you say be consistent in the program.
Do you have a project in mind.?

Eric

 

Hi Eric,

I am still new to PIC and while reading up on SPI I came across this.

"over the years, there have been no consensus on the exact polarity of the SCK signal, the number of bits in a transaction (8 and 16) and where exactly (which edge)the input sampling should happen...."

I am simply trying to understand the effects of choosing one over the other? And how others are making their choice. Is it a requirement by a peripheral or a configuration? etc.

Thanks for your input

 

hi,
As I understand it, the SPI 'industry standard' is set by Freescale [Motorola] , which most peripheral IC manufacturers follow, however some manufacturers use the opposite polarity for their signal levels.

This Freescale PDF explains why there are two choices for polarity.
E

 

Basically, you match the master and slave protocols.

 

The original question was why this should be the case. The answer is flexibility and evolution. Since Motorola designed the initial units that made use of the interface I'm guessing there were implementations that required different configurations to use existing discrete MSI parts. From that point, the LSI peripherals and processors that followed incorporated the flexibility because it had a minimal cost impact on the implementation.

 

The original choice between high and low signals depended on the technology being employed, TTL vs CMOS, noise immunity, open-collector vs tri-state, pull-up vs pull-down, capacitance, clock frequency, etc.

The bottom line is to improve on reliability.

 

Thank you for all your valuable feedback.