The on-state resistance is typically around 125Ω, allowing for 150mA current per circuit without significant voltage drop.

Really?

150 mA through 125 ohms is a voltage drop of almost 19 V. That is beyond the device's ratings. AND, the 4066 power dissipation would be over 300 mW per circuit.

The 4066's relatively high "on" resistance makes it impractical for many applications, especially as an output driver.

ak

 

The CD4066 quad bilateral switch IC is ideal for powering 7 separate circuits sequentially due to its ability to handle voltage and current levels. It can handle up to 15V digital or ±7.5V peak-to-peak analog signals, covering 12V power supply requirements. The on-state resistance is typically around 125Ω, allowing for 150mA current per circuit without significant voltage drop. Implementing this design requires a 555 timer IC, connecting the 12V power supply to the input and output pins, and controlling the switches.

I suppose CD4066 could only be used for low power applications that is what I found out when I researched it. I agree with AnalogKid.

 

Can you recommend a budget chip? The project is mostly proof of concept so I'm looking to get the most bang for my buck while focusing on a single model. The idea is to write a crypto hashing algorithm that is shared between the devices. You may have heard of "lotto miners" so I'll be building on the Esp32 github repos that are available. I might even go hardcore and write from scratch which is an extensive but worthwhile learning project.

What are your criteria re 'budget' - I/O, RAM, Flash, # cores, CPU Speed, etc. etc. ? How is this 'parallelization' going to work? Shared memory, distributed work queues, or what?

Also, do you put your projects on the internet? I'd definitely take a look!

Not the commercial ones, usually for NDA/Copyright issues. Most clients want IP rights etc. But they all have an underlying common design based on an ESP32-S2-VROOM module, though I'm updating for an S3 and thinking about making that a more ruggedised generic device.

Many of the ideas you'll see in my posts on AAC. I have several projects I could blog, if I can ever find the time:
a wi-fi enabled, 6-zone, intelligent wiring centre for heating/hotwater,
a BT-enabled battery monitoring system for my 8S LFP wheelchair battery,
a BT-enabled retrofit controller for a hospital weighbridge,
an experimental 2400W 24v/100A LFP battery charger/balancer/e-load

 

The CD4066 quad bilateral switch IC is ideal for powering 7 separate circuits sequentially due to its ability to handle voltage and current levels. It can handle up to 15V digital or ±7.5V peak-to-peak analog signals, covering 12V power supply requirements. The on-state resistance is typically around 125Ω, allowing for 150mA current per circuit without significant voltage drop. Implementing this design requires a 555 timer IC, connecting the 12V power supply to the input and output pins, and controlling the switches.

Not sure which data sheet you're looking at but TI's version absolute max ±20mA and recommended for continuous operation ±10mA

 

What are your criteria re 'budget' - I/O, RAM, Flash, # cores, CPU Speed, etc. etc. ? How is this 'parallelization' going to work? Shared memory, distributed work queues, or what?


Not the commercial ones, usually for NDA/Copyright issues. Most clients want IP rights etc. But they all have an underlying common design based on an ESP32-S2-VROOM module, though I'm updating for an S3 and thinking about making that a more ruggedised generic device.

Many of the ideas you'll see in my posts on AAC. I have several projects I could blog, if I can ever find the time:
a wi-fi enabled, 6-zone, intelligent wiring centre for heating/hotwater,
a BT-enabled battery monitoring system for my 8S LFP wheelchair battery,
a BT-enabled retrofit controller for a hospital weighbridge,
an experimental 2400W 24v/100A LFP battery charger/balancer/e-load

I don't really have any requirements as the project is mostly about making the most out of each chip.

I'll be mining CPU based alt-coins so processor speed, cache and to a lesser extent RAM are important.

As for resource sharing, I have two paradigms I want to try. The first is to use one chip to communicate with the mining pool server with the rest of the array computing hashes in round robin order. How this will work I don't know as I've only hashed with a single core so far.

The second paradigm is to have the master chip aquire data about which coins are currently best to mine then delegate to the available slaves. This may result in each slave mining a different coin or 50/50 mix etc.

In both cases I want the master to be compatible with n slaves because the long term goal is to get into GPU based mining with a custom control system.

 

Digital "mining" does not provide any REAL value, although it tends to provide money for the miners. AND, worse yet, if hogs a whole lot of power that could be used for better purposes.

 

As for resource sharing, I have two paradigms I want to try. The first is to use one chip to communicate with the mining pool server with the rest of the array computing hashes in round robin order. How this will work I don't know as I've only hashed with a single core so far.

The second paradigm is to have the master chip aquire data about which coins are currently best to mine then delegate to the available slaves. This may result in each slave mining a different coin or 50/50 mix etc.

For both paradigms the key question is how much data & how often. My immediate gut reaction would be to use the 2nd hardware SPI bus to communicate, either as the Master pushing packets of data out to the slaves, or the slaves competing to pull data from the master. Or use a CANBus-like approach which is all 'masters' pushing out messages requesting work, offering work, or offering 'full or partial results'. Lets say there are 3 types of task A, B, C, represented by bits 0,1,2 of a message. And message 0xAn1 is 'give me work of type A', 0xAn2 'of type B', 0xAn3 'of types A or B', and so on... where n is the node ID then any device could transmit 'here is work type A for node X' as 0xBn1ddddddddd. Will need a bit more thinking about.


Anyway, let's not hijack this thread anymore than we have already... maybe you should start your own thread on the subject...