The switch I'm using (DG212) has a capacitance of 5pF and a resistance of 115 ohms. I don't know how to simulate this switch in LTspice.

Now I need to understand the whole picture here. I have an input of 0.89 V to 1.51V into the switch. A logic input is needed to control the switch, which comes in the form of the 5 V pulse running at 750 kHz. When the switch closes the hold capacitor charges. When the switch opens, the capacitor discharges into the switch and the second op-amp. I'm not quite seeing what you are trying to explain. I've almost got it though. I didn't see a threshold voltage for this switch, unless I missed it someplace on the datasheet.

Thank you.

 

I'm not quite seeing what you are trying to explain.

I was explaining gating using a standard MOSFET. However, if you use a DG212 instead, then you could model it something like this :

 

Thank you for showing me how to model the switch. I got that working. I'm just puzzled by C3. What does it do?

My understanding of the rest of the circuit is, the size of the hold capacitor depends on how long the switch is closed for. If the hold capacitor is too large, it will not fully charge and if it's too small, it will fully charge, but there will be excess charge. What I don't know is what happens in either of those conditions.That's the kind of picture I'm looking for.

Thanks,
Mike

 

C3 models the S-to-D channel capacitance, as per my understanding of the DG212 datasheet.

What I don't know is what happens in either of those conditions.That's the kind of picture I'm looking for.

Just play with the Chold value and LTspice will tell you.

 

Alright, I played around with the capacitor values. I used a sine wave input with a DC offset of 1.2V and a swing of 310mV. When I ran it with the 10nF cap I noticed a huge phase shift in the output, but a pretty steady hold value. Smaller capacitor values decreased the phase shift, but increased the error in the held voltage. It's obvious I need to compromise between phase shift and error in the held voltage. I'm already seeing some phase shift in the op-amps caused by parasitic capacitance in the breadboard. That's something I believe I can partly eliminate with a good PCB design, but I have no idea how much till I design one. I don't know how much phase shift is acceptable in a sample and hold for a SAR ADC. I've calculated that I need less than 20mV error in the sampled voltage because this will be an 8-bit ADC (5/2^8 = about 20mV). I currently have about 8-9mV error in each op-amp with a 100 kHz sine input. Added together, that's about 18mV error so I don't have much room for more voltage error. My thinking is I just need to adjust the timing in the rest of the ADC to account for the phase shift, but I don't know if this is the right thinking. I've attached a screenshot of the simulation with a 500pF capacitor. The blue is the input and the green is the output.