Sample and Hold LTspice Simulation

Thread Starter


Joined Sep 1, 2018
I'm using the sample/hold block in LTspice.
As shown in the attached pictures and LTspice simulation, the output has not the same amplitude of the input.
For example, the input amplitude is 60kV while the output is 70V.Screen.png

Can you explain me why?

Thank you.



Joined Mar 14, 2008
I found this here:

SampleHold (aka Sample)
The Sample & Hold symbol is located in the Special Functions symbol folder.

An example schematic, S&H.asc, is located in the Examples/Educational schematic folder.

The behavioral a-device Sample and Hold has two modes of operation. The output may follow the input whenever the S/H input is true or the output may latch to the input when the CLK input goes true. Note that one and only one of these two inputs must be connected.

Parameters unique to the Sample and Hold a-device are as follows:

  • Rout defaults to 1kΩ (instead of the standard a-device 1Ω).
  • Vhigh defaults to 10V and Vlow defaults to -10V (note: these are output voltage saturation levels).
So any input voltage beyond 10V apparently gives flakey results.

Why are are you using such a high input voltage?
No standard sample & hold will operate at those voltages.