You don't need an array of comparators.
A passive or active RC filter will smooth the fluctuations of the sensor output.
If you wish to hold the readout of the LED display you can either use an analog sample and hold circuit or you can latch the digital LED display.

 

You don't need an array of comparators.
A passive or active RC filter will smooth the fluctuations of the sensor output.
If you wish to hold the readout of the LED display you can either use an analog sample and hold circuit or you can latch the digital LED display.

As I said earlier,

A passive integrator will weight later samples more heavily than earlier ones.

You won't get a true average.

 

You don't need an array of comparators.
A passive or active RC filter will smooth the fluctuations of the sensor output.

The comparators are for the display only, like a discrete implementation of a LM3914. The 'hold' part the circuit is so that the display driver can have the the output of the sample without draining the capacitor i.e. to have the signal in voltage remain fixed until for a certain time, or until it is manually disconnected.

A passive integrator will weight later samples more heavily than earlier ones.

Ideally, I would use a passive LPF to smooth the input from the sensor and then connect this to an op-amp integrator (to get a better average) to read the effective value from the sensor for a period of time and then 'hold' the voltage for the display driver.

 

So, are there any methods of holding an analog voltage, without letting it dissipate with load or time (or only a small amount)?

 

If you read off the voltage on the capacitor with a high impedance FET input op-amp the capacitor will hold the voltage steady for a long time (all relatively speaking).

 

So, are there any methods of holding an analog voltage, without letting it dissipate with load or time (or only a small amount)?

Yes. It's called a "sample and hold" circuit because it holds the reading.

 

If I do use a (FET) op-amp with a high Z_in as a buffer, how do I calculate the 'hold' time? I don't really wan't the voltage to 'slide' back down because it will mean that my display module will show the sensor reading falling, unless there is a way to 'save' the peak output?
It would fine if the voltage could hold constant for a while and then fall quickly.

 

FET op amps have input impedances of the order of 10^12 ohms.
With a 1μF filter capacitor the time constant will be very long. You don't have to worry about leakage.

 

I think an integrator is your best bet.
The problem with the conventional integrator is that it's inverting. You wind up needing dual (±) power supplies.
Check out the Deboo integrator (see attached simulation). It is noninverting, so you can use a single 5V supply,if you choose a rail-to-rail I/O op amp. I have added a lot of noise to the input, as you can see. I integrated the input over 3 seconds. The final output voltage is scaled so that the output will be the true integral of the input over the 3 second interval. It will hold that voltage with very little change for a long time, assuming you choose a zero bias current (CMOS) input op amp, and a low-leakage, low dielectric absorption capacitor (polypropylene or polystyrene).
You can use a 74HC or 74HCT4066 for the switches (4 per package).
The only disadvantage that I can see is that you cannot easily adjust the integration time constant to compensate for component tolerances. You might need a second op amp to make this adjustment
The common inverting integrator and be adjusted using a single adjustable resistor (rheostat).

 

I'm having a look at your circuit now, but I can't seem to get it to work (I'm using TINA for my simulations what are you using?), how do those summing points work?
I think I will go with an integrator, but I've never seen a "Deboo" Integrator before, so I'm quite unfamiliar with it.

In regard to the 'hold' capacitor, is 1uF sufficient/what determines the cap size in a s&h circuit?

 

I'm having a look at your circuit now, but I can't seem to get it to work (I'm using TINA for my simulations what are you using?), how do those summing points work?
I think I will go with an integrator, but I've never seen a "Deboo" Integrator before, so I'm quite unfamiliar with it.

In regard to the 'hold' capacitor, is 1uF sufficient/what determines the cap size in a s&h circuit?

The simulator is LTspice. It's free and uncastrated, and is very popular on this forum.
The capacitor in a S&H (not in an integrator) should generally be as large as possible and still be capable of being fully charged within the width of the sample pulse. This is because a larger cap will generally have less droop in the hold mode, and will be subject to less feedthrough from the signal source and less charge injection from the switching signal. The charging time is limited by the resistance of your sampling switch and/or the current sourcing/sinking capability of your signal source.
"Fully charged" is something you have to define. It depends on the accuracy you require. An RC circuit charges following this equation:

\(V=V_s\cdot e^-\frac{T}{R\cdot C}\)

So, if you can live with:

1% error, RC < T/4.6
0.1% error, RC < T/6.9
.01% error, RC < T/9.2
etc., etc.

Where R is switch + source resistance, C is your hold capacitance, and T is the sample pulse width.

 

As a general rule of thumb if you wait for 6 time constants that will get you to about 0.25% error which ought to be good enough in many applications.

 

Thanks for that! I'm trying to run your simulation, but it seems to be running a noise analysis (I'm getting a number of variable outputs), how do I change this to a nominal output (like your example in post #29)? Also, how do those switches work...?
We've also tried to create a similar circuit in TINA based on this page, but the V_out is offset and doesn't start at 0v.

 

Thanks for that! I'm trying to run your simulation, but it seems to be running a noise analysis (I'm getting a number of variable outputs), how do I change this to a nominal output (like your example in post #29)? Also, how do those switches work...?
We've also tried to create a similar circuit in TINA based on this page, but the V_out is offset and doesn't start at 0v.

I don't do Tina, and I don't see myself paying for it.
If you downloaded LTspice, and ran the .asc file I posted, then you should get the same results I got.
LTspice has an pretty good help file. It tells how to probe nodes and branches. It explains voltage-controlled switches (sw element). If you study the help file, and still can't figure things out. come back with questions.

 

I don't do Tina, and I don't see myself paying for it.

We were only taught using TINA, but it's not the best choice I admit. I am using the free (and reduced) version TINA-TI. Am I right in saying that with S1 the switch shorts to ground when V(rst) is logic high (and is floating/disconnected otherwise)? Similarly, with S2 which closes when V(track) goes high, but integrates V(track) and V(in)? I don't understand why S3 is needed (I thought it was permanently connected to ground?), unless it is used to discharge the integrator?

Anyway, you can see from the picture what happens when I run your file. I've managed to figure some of LTspice out, but there are still a lot of grey areas. We have manged to get results using a integrator with a virtual ground at Vcc/2, but its a backup and I would prefer to use the Deboo integrator since it gives a much better output voltage range, reduces the circuits overall complexity and doesn't give an inverted signal. Our tests seemed to show the output voltage being quite stable with a restive load, so does this mean the integrator output doesn't need to be buffered (assuming the use of a CMOS opamp)?

 

We were only taught using TINA, but it's not the best choice I admit. I am using the free (and reduced) version TINA-TI. Am I right in saying that with S1 the switch shorts to ground when V(rst) is logic high (and is floating/disconnected otherwise)? Similarly, with S2 which closes when V(track) goes high, but integrates V(track) and V(in)? I don't understand why S3 is needed (I thought it was permanently connected to ground?), unless it is used to discharge the integrator?

Anyway, you can see from the picture what happens when I run your file. I've managed to figure some of LTspice out, but there are still a lot of grey areas. We have manged to get results using a integrator with a virtual ground at Vcc/2, but its a backup and I would prefer to use the Deboo integrator since it gives a much better output voltage range, reduces the circuits overall complexity and doesn't give an inverted signal. Our tests seemed to show the output voltage being quite stable with a restive load, so does this mean the integrator output doesn't need to be buffered (assuming the use of a CMOS opamp)?

A thousand apologies! I posted the wrong .asc file. I have edited post #29 to correct this error.

Switch S3 is needed because, without it, the voltage gain due to R3 and R5 (G=1.033) causes current to continue to flow in R6, which in turn continues to flow into C1, resulting in an exponentially increasing ramp. What we want to happen is for current through C1 to go to zero when we turn Track off, so that the output is held constant until reset. Opening S2 and S3 turns the op amp into a voltage follower. The presence of R6, along with the input offset voltage of the op amp, will result in some tilt in the output voltage over time. You should choose an op amp with low input offset voltage. Adding a switch in series with R6 will also help.
You can see the effect of removing S3 by temporarily placing a ground at the junction of S3 and R3, and rerunning the sim.

Note that the "textbook" Deboo integrator has R5 and R6 equal to R2 and R3 (3Meg in this case). The reason I didn't do this is it makes the output voltage during the integration time go twice as high as the final held value. This means that, with a 5V supply and a rail-to-rail op amp, your usable output range would only be about 0 to 2.5V. With R5 and R6=100k, you can get about 4.8V of usable range. The advantage of making all 4 resistors equal is that the circuit is MUCH less sensitive to input offset voltage, and the presence of R6 when in hold mode. You could also use a higher supply voltage to eliminate the range limitation. These are decisions you have to make.

You don't need a buffer. The op amp IS a buffer.

 

Cheers for that exploitation, but I am am can't seem to get my usable output range up high enough. The best rail to ground supply I can mange is +7v. According to the simulations I have done (using a TL071 JFET op-amp) the maximum V(out) I can achieve is ~5.4v, or ~3.4v using the 5v supply. Any way to improve that (I am using the same resistor and capacitor values)/better op-amp that is rail-to-rail? I am seeing the potential effects of the offset voltage too, whereby V(out) rises up to about 1 volt even though V(rst) is HIGH. I would have thought that the capacitor being grounded would have stopped this?

In regard to adjusting the integration time constant to compensate for component variation, you suggested that this would be possible using a separate op-amp. I am curious as to how this could be implemented, and is it done by scaling the input signal prior to integrating?

 

I did tell you earlier that you need a rail-to-rail op amp.

Your output voltage WILL drift with time. You need to take a measurement ASAP after the end of the integration time. A sample-and-hold has the same limitations.
How and when do you intend to make this measurement?
We can't pick an op amp until this is determined.

 

ok, I want to make the measurement <1 second after the integration is completed. I have a signal created with an RC delay that can be used to trigger the process. I was going to just use a capacitor and high input impedance op-amp to buffer the capacitor, then use the output to drive the array of LED's/comparators (to determine how many LED's to light) - but you said that the op amp is the buffer? The output is only going to used/valid for about 5 seconds anyway, so drift and the end buffer don't really affect the results by the looks of my simulations.

 

Instead of comparators just use an LM3914 bar LED display driver.