I have a general question about reverse voltage protection. For most of my designs that involve some moderate power, I tend to use the PMOS on the high side with a zener to clamp and protect it. My question is about the other transistors in the circuit and how the pullups and pulldowns are affected by reverse battery. If I have a NMOS turning on a load and use the traditional pull down resistor, the reverse orientation would tie it to the input voltage. Now there is no ground since the PMOS never is turned on to protect against this but I just wanted to make sure I am right with that assumption. There is no way that a pullup and pulldown can activate the transistor with a PMOS reverse protection scheme correct?

 

Without a schematic or even a block diagram your description is very difficult to follow. While the idea of a pullup resistor iw well known, it's location in a circuit can be anywhere.

ak

 

If no power supply is connected, it can't be backwards. The answer lies in how perfectly the PMOS refuses battery current. If the load (circuit) can't access enough voltage to turn on a diode junction, you are safe.

 

This is a basic example in the normal orientation. Q2 would be driven by a microcontroller that would be after the PMOS. So if this circuit was hooked up backwards the ground would be floating because the PMOS would never connect it to ground. Is this correct?

 

Your example is one of extremes, no defined load. Microcontrollers do not have information about their current draw under very small voltages. If you look up the reverse leakage of the PMOS at the highest temperature expected, you can add a load resistor to be sure some few microamps will not develop enough voltage to do any harm. For instance, 50k ohms will dissipate 10 ua to common when 0.5 volts are available.

As usual, one experimental result is worth a dozen theories. When in doubt, measure it.

 

Q1 looks backwards. A MOSFET is controlled by Vgs, not Vgd. You are relying on the forward biasing of the internal zener diode to establish a voltage relationship from Source to Drain (GND). I guess it will work, but it just doesn't look right somehow.

ak

 

this will help.

 

Q1 looks backwards. A MOSFET is controlled by Vgs, not Vgd. You are relying on the forward biasing of the internal zener diode to establish a voltage relationship from Source to Drain (GND). I guess it will work, but it just doesn't look right somehow.

The connection of the P-MOSFET (Q1) is correctly orientated for reverse bias protection.
MOSFETs conduct equally well in both directions so when a positive voltage is applied to the P-MOSFET's drain with the gate grounded it will fully turn on and conduct the load current. The substrate diode is also forward biased under this condition but conducts no current (except perhaps during turn on) since its forward voltage is greater then the MOSFET ON voltage from drain to source.
If a reverse (negative) input voltage is applied to Q1's drain, the transistor will stay off since the drain-gate voltage is zero and the substrate diode is reverse biased.

 

Yeah, I know all that; I wasn't saying it is backwards, just looks backwards. And while I prefer N-channel devices in the return leg for this function, I've designed them in in both directions based on other circuit requirements. Still, if you think of a PNP device acting as a switch device in the positive rail, you grow up thinking that the emitter (source) is the input and the collector (drain) is the output. A MOSFETs on-state bidirectionality expands the rules, but still...

ak

 

Yeah, I know all that; I wasn't saying it is backwards, just looks backwards. And while I prefer N-channel devices in the return leg for this function, I've designed them in in both directions based on other circuit requirements. Still, if you think of a PNP device acting as a switch device in the positive rail, you grow up thinking that the emitter (source) is the input and the collector (drain) is the output. A MOSFETs on-state bidirectionality expands the rules, but still...

Well, you seemed uncertain as to whether it would work in your post #6, hence the explanation.
My apologies if I misunderstood.

 

No prob. But I am disappointed that you didn't whip up six LTSpice simulations.

 

No prob. But I am disappointed that you didn't whip up six LTSpice simulations.

I was feeling lazy.
Anyway my limit is usually one simulation per post.