Resistor function and values for RS422 driver output

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3278User

Joined May 4, 2020
6
Hello - New to this website and forum and hoping that I have posted in the correct location. I have a question on the attached diagram from a datasheet for an IBM protocol converter chipset (DP8340 Transmitter and DP8341 Receiver). These two chips work in conjunction with a DS3487 Quad Tri-State Line driver to connect to coax line to transmit and receive data. The receiver simply connects to the coax via the 1:1:1 transformer. However, the transmitter as shown in the sample application uses several resistors (R1 thru R5) before going to the transformer. The Data Delay and Data lines are inverse of each other and driven by the output of the transmitter. I understand pin 4 controlling the Hi-Z state but do not understand the function and values of the resistors. I have a very rudimentary understanding of electronics and I am trying to understand the purpose of the resistors. From the chipset datasheets, the Data Delay and Data (inverted) appear to be identical but inverted. So I am confused on the not only the purpose of the resistors, but also why the difference in chosen values of 150 for Data and 33 for the Data Delay logic. My guess on the receiver is that the resistance values may be built into the chip and that is why there is a direct connection to that chip from the coax. I would like to understand the concept prior to building, instead of simply assembling components. Thank you for your time in reviewing this post and I very much appreciate any helpful information.
 

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Papabravo

Joined Feb 24, 2006
13,721
This is just a guess, but since transformers are inherently AC-only devices, it seems like a method of converting an NRZ data input into pulses. Allen-Bradley Data Highway and some of their other proprietary networks used transformer coupling, and circuits like this to prevent the DC component from long string of identical symbols, either 1's or 0's, from building up a positive or negative bias on the network cable. The problem with charging the cable up with either a positive or negative bias is that it has to be discharged before it starts affecting the values of subsequent bits.
 

Thread Starter

3278User

Joined May 4, 2020
6
Thank you for the info. Your guess sounds like a solid reason behind the AC. But I'm still confused at the function and chosen values of the resistors. From what I have read on the use of the chipset, the coax signal is using Manchester encoding. I understand the basics a little bit but still cannot see how the small resistor network is used or why it is needed. Escpecially when the receiver chip takes the data straight from the coax input. Very confusing at this stage. Thanks again for your reply.
 

Papabravo

Joined Feb 24, 2006
13,721
Think of the cable as a large value distributed capacitor. That the data is Manchester encoded is not a surprise. The differential resistors might be related to differing time constants for charging an discharging the cable. The 510 Ω resistor across the transmit coil is to allow the signal on that side of the transformer to decay when there are no more signal transitions. You might want to try a spice simulation of the transformer and the resistor networks to see if that provides any insight.

One other clue to look for is the maximum run length of a single symbol, either a 1 or a 0, before bit stuffing occurs.
 

Thread Starter

3278User

Joined May 4, 2020
6
Excellent info. I have attached the Datasheet which has some timing diagrams. As I am just starting to get into more than basic electronics, I am not sure of all of the info on the datasheets (like the timing diagrams). I understand basic pinouts and logic levels but this chip threw me for a loop. You are 100% correct on the delay line. There is some type of discrepancy. At first I thought it followed the Data line but it seems to be offset. The coax line goes from an old 3278 Green Screen terminal to a controller unit (talking to a bunch of 3278 terminals and passing on the info to a mainframe). I am trying to get the 3278 talking to a linux box as regular terminal using the DP8340/41 chipset (and handling the software end once I can get data coming across the coax. This has been done before with boards in PCs, but they use very complicated single chips that handle everything using 60+ pins. I am tyring to take it at a very basic level using earliest chipset that handle the task. Trying to save an iconic IBM terminal and repurpose it. Thanks for your input here.
 

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Thread Starter

3278User

Joined May 4, 2020
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The one items I kept reading but it still doesn't make sense is (on page 2-5):
"The Data outputs are a direct bit representation of the biphase data while the DATA DELAY output provides
the necessary increment to clearly define the four (4) DC levels of the pulse."
No sure what are four levels, because normally there are only 2 logic levels (I am missing something here).
 

Papabravo

Joined Feb 24, 2006
13,721
The one items I kept reading but it still doesn't make sense is (on page 2-5):
"The Data outputs are a direct bit representation of the biphase data while the DATA DELAY output provides
the necessary increment to clearly define the four (4) DC levels of the pulse."
No sure what are four levels, because normally there are only 2 logic levels (I am missing something here).
Yes you are. Using four levels allows for the ability to move more data through a slow channel. Now you need to look at adjacent doublets. The following sequences would all look different on the wire
  1. 00
  2. 01
  3. 10
  4. 11
I don't know the details, but I did work on a network with 3-levels once.
 

Thread Starter

3278User

Joined May 4, 2020
6
They reference a timing chat (Fig 15) yet that has nothing to do with Data or Data Delay. Is it possible that the datasheet is incorrect? I have read it several times and the figure they refer to only deals with two other pins/signals. Odd indeed.
 

Papabravo

Joined Feb 24, 2006
13,721
They reference a timing chat (Fig 15) yet that has nothing to do with Data or Data Delay. Is it possible that the datasheet is incorrect? I have read it several times and the figure they refer to only deals with two other pins/signals. Odd indeed.
No the datasheet is correct. You should focus on Figures 4 & 5. Figure 4 is for a single byte transfer. Notice the thin vertical lines between the waveforms. Those are the actual bit boundries. The data bits are actually in bits 2 through 9 and are defined by looking at all three levels of DATA, DATA-BAR, and DATA DELAY. The squiggly lines in the waveforms are for bits 3 through 8.
Moving to figure 5 for the transfer of more than 1 byte of data you can see a slight modification of the single byte protocol.

Figure 15 refers to the signals at the top of the timing diagram in Figs 4 & 5 called REG-LOAD-BAR and TA

Hope this helps
 
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